Unify the bin scripts into one Python script with equiv checking

[jk2997]

@matth2k simlib.v defines FDRE as:

module FDRE #(
    parameter INIT = 0
) (
    input  C,
    input  CE,
    input  D,
    input  R,
    output Q
);
  reg q;
  always @(posedge C) begin
    if (CE) begin
      if (R) begin
        q <= INIT;
      end else begin
        q <= D;
      end
    end
  end
endmodule

Because this is a process, without proc, yosys returns the error ERROR: Gold module contains memories or processes. Run 'memory' or 'proc' respectively. when running equiv.sh on Verilog modules that contain FDRE.

[matth2k]

Thanks! I'll play around with this once we get some of the sequential benchmarks compiling (still some wrinkles to iron out).

[jk2997]

@matth2k I have unified the bin scripts into one Python script. The Python script runtool.py comes with an additional script runtool that allows commands with the format runtool [subcommand] [input.v] [output.v] [options] to be executed after source utils/setup.sh is done. The Python script also does equiv.sh [unsynthesized input .v file] [EqMap output .v file] at the end of each subcommand (eqmap, eqmap_vivado, lvv, etc). I also decided to enforce an output .v file, since otherwise the terminal would be flooded by the equiv checking output immediately after the EqMap is written to stdout, making the EqMap stdout output inconvenient to read.