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Support Xilinx SRL16E & FDSE primitive

Status: Open.

#207 In cornell-zhang/eqmap;

· matth2k opened on Feb 20, 2026

opt-verilog returns an index-out-of-bounds error for some netlists

Status: Open.

#205 In cornell-zhang/eqmap;

· jk2997 opened on Feb 20, 2026

Deprecate verilog parsing module and testing tools

Status: Open.

#204 In cornell-zhang/eqmap;

· matth2k opened on Feb 20, 2026

Better Greedy Extraction Metric

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

#75 In cornell-zhang/eqmap;

· jku20 opened on Dec 12, 2024

Yosys version has large impact on results

good first issueGood for newcomersGood for newcomers

Status: Open.

#74 In cornell-zhang/eqmap;

· matth2k opened on Dec 11, 2024

Support for sequential logic

good first issueGood for newcomersGood for newcomers

Status: Open.

#13 In cornell-zhang/eqmap;

· matth2k opened on Nov 4, 2024