Enhancing cosimulation

tools/dynamatic/dynamatic.cpp

@@ -70,6 +70,9 @@ static cl::opt<bool> exitOnFailure(
         "If specified, exits the frontend automatically on command failure"),
     cl::init(false), cl::cat(mainCategory));
 
+static constexpr llvm::StringLiteral VHDL("vhdl");
+static constexpr llvm::StringLiteral VERILOG("verilog");
+
 namespace {
 enum class CommandResult { SYNTAX_ERROR, FAIL, SUCCESS, EXIT, HELP };
 } // namespace
@@ -92,12 +95,12 @@ struct FrontendState {
   std::string dynamaticPath;
   std::string vivadoPath = "/tools/Xilinx/Vivado/2019.1/";
   std::string fpUnitsGenerator = "flopoco";
+  llvm::StringLiteral hdl = VHDL;
   // By default, the clock period is 4 ns
   double targetCP = 4.0;
   std::optional<std::string> sourcePath = std::nullopt;
   std::string outputDir = "out";
 
-
   FrontendState(StringRef cwd) : cwd(cwd), dynamaticPath(cwd) {};
 
   bool sourcePathIsSet(StringRef keyword);
@@ -268,14 +271,16 @@ class SetCP : public Command {
 class SetOutputDir : public Command {
 public:
   SetOutputDir(FrontendState &state)
-      : Command("set-output-dir", "Sets the name of the dir to perform HLS in. If not set, defaults to 'out'", state) {
+      : Command("set-output-dir",
+                "Sets the name of the dir to perform HLS in. If not set, "
+                "defaults to 'out'",
+                state) {
     addPositionalArg({"out_dir", "out dir name"});
   }
 
   CommandResult execute(CommandArguments &args) override;
 };
 
-
 class Compile : public Command {
 public:
   static constexpr llvm::StringLiteral FAST_TOKEN_DELIVERY =
@@ -646,7 +651,8 @@ CommandResult SetOutputDir::execute(CommandArguments &args) {
   llvm::StringRef outputDir = args.positionals.front();
 
   // reject trivial bad cases
-  if (outputDir.empty() || outputDir == "." || outputDir == ".." || outputDir.endswith("/"))
+  if (outputDir.empty() || outputDir == "." || outputDir == ".." ||
+      outputDir.endswith("/"))
     return CommandResult::FAIL;
 
   // reject illegal chars
@@ -733,6 +739,7 @@ CommandResult WriteHDL::execute(CommandArguments &args) {
   if (auto it = args.options.find(HDL); it != args.options.end()) {
     if (it->second == "verilog") {
       hdl = "verilog";
+      state.hdl = VERILOG;
     } else if (it->second == "verilog-beta") {
       hdl = "verilog-beta";
     } else if (it->second == "smv") {
@@ -764,15 +771,28 @@ CommandResult Simulate::execute(CommandArguments &args) {
     } else {
       llvm::errs() << "Unknow Simulator '" << it->second
                    << "', possible options are 'ghdl', "
-                      "'xsim', and 'vsim'.\n";
+                      "'xsim', 'vsim' and 'verilator'.\n";
       return CommandResult::FAIL;
     }
   }
 
+  if (simulator == "ghdl" && state.hdl != VHDL) {
+    llvm::errs() << "Simulator 'ghdl' is not compatible with this HDL. Use "
+                    "'vsim', 'xsim' or 'verilator'. \n";
+    return CommandResult::FAIL;
+  }
+
+  if (simulator == "verilator" && state.hdl != VERILOG) {
+    llvm::errs()
+        << "Simulator 'verilator' is not compatible with this HDL. Use "
+           "'vsim', 'xsim' or 'ghdl'. \n";
+    return CommandResult::FAIL;
+  }
+
   return execCmd(script, state.dynamaticPath, state.getKernelDir(),
                  state.getOutputDir(), state.getKernelName(), state.vivadoPath,
                  state.fpUnitsGenerator == "vivado" ? "true" : "false",
-                 simulator);
+                 simulator, state.hdl);
 }
 
 CommandResult Visualize::execute(CommandArguments &args) {
@@ -960,4 +980,4 @@ int main(int argc, char **argv) {
     free(rawInput);
   }
   return 0;
-}
+}

tools/dynamatic/scripts/simulate.sh

@@ -14,6 +14,7 @@ KERNEL_NAME=$4
 VIVADO_PATH=$5
 VIVADO_FPU=$6
 SIMULATOR_NAME=$7
+HDL_TYPE=$8
 
 # Generated directories/files
 SIM_DIR="$(realpath "$OUTPUT_DIR/sim")"
@@ -63,11 +64,19 @@ cp "$SRC_DIR/$KERNEL_NAME.c" "$C_SRC_DIR"
 cp "$SRC_DIR/$KERNEL_NAME.h" "$C_SRC_DIR" 2> /dev/null
 
 # Copy TB supplementary files (memory model, etc.)
-cp "$RESOURCE_DIR/templates_vhdl/template_tb_join.vhd" "$COSIM_HDL_SRC_DIR/tb_join.vhd"
-cp "$RESOURCE_DIR/templates_vhdl/template_two_port_RAM.vhd" "$COSIM_HDL_SRC_DIR/two_port_RAM.vhd"
-cp "$RESOURCE_DIR/templates_vhdl/template_single_argument.vhd" "$COSIM_HDL_SRC_DIR/single_argument.vhd"
-cp "$RESOURCE_DIR/templates_vhdl/template_simpackage.vhd" "$COSIM_HDL_SRC_DIR/simpackage.vhd"
-cp "$RESOURCE_DIR/modelsim.ini" "$HLS_VERIFY_DIR/modelsim.ini"
+if [ "$HDL_TYPE" = "verilog" ]; then
+  cp "$RESOURCE_DIR/templates_verilog/template_tb_join.v" "$COSIM_HDL_SRC_DIR/tb_join.v"
+  cp "$RESOURCE_DIR/templates_verilog/template_two_port_RAM.v" "$COSIM_HDL_SRC_DIR/two_port_RAM.sv"
+  cp "$RESOURCE_DIR/templates_verilog/template_single_argument.v" "$COSIM_HDL_SRC_DIR/single_argument.sv"
+  cp "$RESOURCE_DIR/modelsim.ini" "$HLS_VERIFY_DIR/modelsim.ini"
+  cp "$RESOURCE_DIR/verilator_main.cpp" "$HLS_VERIFY_DIR/verilator_main.cpp"
+else
+  cp "$RESOURCE_DIR/templates_vhdl/template_tb_join.vhd" "$COSIM_HDL_SRC_DIR/tb_join.vhd"
+  cp "$RESOURCE_DIR/templates_vhdl/template_two_port_RAM.vhd" "$COSIM_HDL_SRC_DIR/two_port_RAM.vhd"
+  cp "$RESOURCE_DIR/templates_vhdl/template_single_argument.vhd" "$COSIM_HDL_SRC_DIR/single_argument.vhd"
+  cp "$RESOURCE_DIR/templates_vhdl/template_simpackage.vhd" "$COSIM_HDL_SRC_DIR/simpackage.vhd"
+  cp "$RESOURCE_DIR/modelsim.ini" "$HLS_VERIFY_DIR/modelsim.ini"
+fi
 
 # Compile kernel's main function to generate inputs and golden outputs for the
 # simulation
@@ -89,6 +98,7 @@ if [ "$VIVADO_FPU" = "true" ]; then
   --kernel-name="$KERNEL_NAME" \
   --handshake-mlir="$OUTPUT_DIR/comp/handshake_export.mlir" \
   --simulator="$SIMULATOR_NAME" \
+  --hdl="$HDL_TYPE" \
   --vivado-fpu \
   > "../report.txt" 2>&1
 else
@@ -97,6 +107,7 @@ else
   --kernel-name="$KERNEL_NAME" \
   --handshake-mlir="$OUTPUT_DIR/comp/handshake_export.mlir" \
   --simulator="$SIMULATOR_NAME" \
+  --hdl="$HDL_TYPE" \
   > "../report.txt" 2>&1
 fi
-exit_on_fail "Simulation failed" "Simulation succeeded"
+exit_on_fail "Simulation failed" "Simulation succeeded"

tools/hls-verifier/hls-verifier.cpp

@@ -140,9 +140,16 @@ int main(int argc, char **argv) {
       cl::value_desc("vivado-fpu"), cl::init(false));
 
   cl::opt<std::string> simulatorType(
-      "simulator", cl::desc("Simulator of choice (options: xsim, ghdl, vsim)"),
+      "simulator",
+      cl::desc("Simulator of choice (options: xsim, ghdl, vsim, verilator)"),
       cl::value_desc("Simulator of choice"), cl::init("vsim"));
 
+  cl::opt<std::string> hdlType("hdl",
+                               cl::desc("HDL used for simulation. Can either "
+                                        "be 'vhdl' (default) or 'verilog'"),
+                               cl::value_desc("HDL for simulation"),
+                               cl::init("vhdl"));
+
   cl::ParseCommandLineOptions(argc, argv, R"PREFIX(
     This is the hls-verifier tool for comparing C and VHDL/Verilog outputs.
 
@@ -178,7 +185,9 @@ int main(int argc, char **argv) {
   handshake::FuncOp funcOp =
       dyn_cast<handshake::FuncOp>(modOp->lookupSymbol(hlsKernelName));
 
-  VerificationContext ctx(simPathName, hlsKernelName, &funcOp, vivadoFPU);
+  HdlType hdl = (hdlType == "verilog") ? VERILOG : VHDL;
+
+  VerificationContext ctx(simPathName, hlsKernelName, &funcOp, vivadoFPU, hdl);
 
   // Generate hls_verify_<hlsKernelName>.vhd
   vhdlTbCodegen(ctx);
@@ -191,6 +200,8 @@ int main(int argc, char **argv) {
     simulator = std::make_unique<VSimSimulator>(&ctx);
   } else if (simulatorType == "xsim") {
     simulator = std::make_unique<XSimSimulator>(&ctx);
+  } else if (simulatorType == "verilator") {
+    simulator = std::make_unique<Verilator>(&ctx);
   } else {
     logErr(LOG_TAG, "Wrong Simulator (use vsim, xsim, ghdl, verilator)");
     return 1;
@@ -211,4 +222,4 @@ int main(int argc, char **argv) {
     return 1;
   }
   return 0;
-}
+}