Enhancing cosimulation #696
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Jiahui17
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Jan 6, 2026
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| vector<string> fileListSystemVerilog = | ||
| getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".sv"); |
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Could we remove sv for now? I don't think we generate any SV files
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Could you rename 'single_argument' to *.sv
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| os << "--exe verilator_main.cpp --trace-underscore --Wno-UNOPTFLAT " | ||
| "--top-module tb --timing -Wno-REALCVT\n"; |
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Print also the meaning of the flags as comments in the SH file: what are --trace-underscore, --Wno-UNOPTFLAG, and -Wno-REALCVT
Jiahui17
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Jan 7, 2026
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| cp "$RESOURCE_DIR/templates_verilog/template_two_port_RAM.v" "$COSIM_HDL_SRC_DIR/two_port_RAM.sv" | ||
| cp "$RESOURCE_DIR/templates_verilog/template_single_argument.v" "$COSIM_HDL_SRC_DIR/single_argument.sv" |
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Leave a note why this file is SV
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Added testbenches in verilog
Added Verilator