GitHub - 1RyanChen1/UART-Protocol: Universal Asynchronous Transmitter Receiver(UART) protocol implemented in Verilog HDL, takes clock frequency as 100Mhz, 115200 baud rate and 16 oversample with 8-N-1 frame format

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Universal Asynchronous Transmitter Receiver(UART) protocol implemented in Verilog HDL, takes clock frequency as 100Mhz, 115200 baud rate and 16 oversample with 8-N-1 frame format

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Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
baud_gen.v		baud_gen.v
top_uart.v		top_uart.v
uart_rx.v		uart_rx.v
uart_tx.v		uart_tx.v

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Universal Asynchronous Transmitter Receiver(UART) protocol implemented in Verilog HDL, takes clock frequency as 100Mhz, 115200 baud rate and 16 oversample with 8-N-1 frame format