Popular repositories Loading
-
UART-Protocol
UART-Protocol PublicUniversal Asynchronous Transmitter Receiver(UART) protocol implemented in Verilog HDL, takes clock frequency as 100Mhz, 115200 baud rate and 16 oversample with 8-N-1 frame format
Verilog 1
-
PDF-Merger
PDF-Merger PublicA free, open source, safe, and fully offline PDF merger tool built by python
Python 1
-
-
-
Restaurant-Management-System
Restaurant-Management-System PublicRestaurant Manegement System that made by Java.
Java
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.