WIP - use voronoi-diagram-for-polygons for partition lines

[usbalbin]

kikit panelize \
    --layout 'alternation: cols; vevendiff: 0mm; rotation: 90deg; rows: 2; cols: 2; baketext: False; hspace: -10mm; vspace: 10mm' \
    --tabs 'type: fixed' \
    --cuts 'type: mousebites' \
    --framing 'type: tightframe; hspace: 2mm; vspace: 2mm; width: 10mm' \
    l.kicad_pcb 'out.kicad_pcb' --debug 'drawPartitionLines: true' && pcbnew 'out.kicad_pcb

This is a of some sort of proof of concept state at this point. I am not too familiar with kikit's internals but as far as I can tell the partition lines does seem to make some sense, right?

I think I might me missing something since the tabs on the left and right towards the panel are missing

[usbalbin]

Running this on a PCB with arcs in the outline or otherwise complex shapes seems to produce a partition line consisting of loads of little segments. This does seem to have quite bad affect on the performance. In one of my tests on one such PCB the panelization took about 200 seconds. Without the normal BB partitioning it would have taken about 10 or so seconds

[yaqwsx]

Thank you for your efforts! The partition line you propose is suitable for tabs placement; however, it is unsuitable for backbones. I started implementing a solution in d7622a1, however, making it roboust is quite challenging.

So we either need to finish the robust solution or make the partition line engine switchable.