MIPS Simulator with three following modes: ***A. Functional simulator *** B. No pipeline forwarding ***C. Pipeline forwarding
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Updated
Feb 4, 2026 - SystemVerilog
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hazard-handling
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Implementation of a 32-bit RISC-V processor in iVerilog, featuring both a sequential datapath and a 5-stage pipeline. Includes a complete hazard detection unit for stalls, a forwarding unit for data hazards, and branch flushing logic.
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Updated
Feb 18, 2026 - Verilog
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