C++ Instruction Set Simulator for RISC-V RV32IMC & custom packed SIMD ISA with cache and branch predictor models, C/ASM workloads, and Python analysis tools

An 8-bit CPU with a custom ISA, designed from scratch in Verilog, and its complete assembler toolchain developed in C++.

Emulator for Computer Organization Course Mini Project

Assember for Computer Organization Course Mini Project

A custom 16-bit MIPS-inspired processor built in Logisim, featuring a unique instruction set, ALU, register file, and memory components. Designed for educational purposes and low-level computing exploration.