tracing why days feel productive or unproductive by inferring structured explanations from passive signals using an explicit ontology.

Verilog implementation of a 4-bit adder/subtractor using combinational logic with testbench and simulation output.

Verilog implementations of a 4-bit adder using behavioral, dataflow, and structural modeling styles, along with corresponding testbenches and block diagrams. This project demonstrates the design and simulation of digital adders as part of an academic lab experiment.