SoC Physical Design & IC Layout Engineer
I focus on delivering physical design and layout that are reliable and reproducible.
I document what I learn, share study guides, and write about the challenges of SoC physical design and IC layout.
Specializing in Analog Hard IPs (HIPs), Custom & Compiler-Generated Memory Macros, and Standard Cell Library Development.
Skilled in STA, P&R, DRC/LVS, and automation scripting to deliver advanced-node designs that meet stringent PPA, reliability, and manufacturing targets.
Over the course of my career, I’ve taken SoC partitions, Analog Hard IPs, and both custom and compiler-generated memory macros from concept to tapeout.
I’ve also designed and implemented multiple standard cell libraries, ensuring every block meets performance, power, area, and manufacturability requirements.
My focus has been on building layouts that balance precision and efficiency, while keeping flows reproducible and sign-off ready.
- Designing SoC floorplans, running place & route, clock tree synthesis, timing closure, and power optimization
- Implementing analog blocks, SRAM/ROM, and custom or compiler-generated memory macros with parasitic extraction
- Verifying designs with STA, DRC/LVS, IR drop, and EM analysis
- Automating flows and checks with TCL, Python, and shell scripting
- Cadence Innovus, Virtuoso, Genus
- Synopsys ICC2, PrimeTime, ICV
- Mentor Calibre
- Other industry-standard EDA tools
| Repository | Description |
|---|---|
| soc-physical-design-notes | SoC physical design workflows, floorplanning, routing, and sign-off notes. |
| ic-layout-notes | Analog & memory IC layout techniques, matching, symmetry, and DRC/LVS tips. |
| tamra-hargus-portfolio | Portfolio of engineering, design, and technical writing projects. |
| writing-portfolio | Articles on SoC design, IC layout, and layout-dependent effects. |