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1. RISC-V-with-Hard-Macro RISC-V-with-Hard-Macro Public

   Developed and integrated hard macros for RISC-V processor sub-modules, optimizing for area, power, and performance. Executed complete physical design flow, including synthesis, floor planning, plac…

   Verilog

2. Router_1X3_PD Router_1X3_PD Public

   Executed the complete physical design flow of a 1x3 router, encompassing synthesis, floorplanning, placement, clock tree synthesis, routing, and static timing analysis using Synopsys Fusion Compile…

   Tcl

3. Router_1X3_RTL Router_1X3_RTL Public

   This repository contains a Verilog HDL implementation of a 1x3 router. The router directs data packets to one of three output ports. It includes modules for FIFO, FSM, registers, synchronization, a…

   1

4. Fire-and-Smoke-Alarm-System Fire-and-Smoke-Alarm-System Public

   Fire Alarm System is designed to alert us to an emergency so that we can take action to protect ourselves from fire or gas leakages

   C++

5. Wall-E Wall-E Public

   Wall-E a line following and self balancing bot

   C