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Adds two new Tier 3 targets - aarch64v8r-unknown-none{,-softfloat}
#150863
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37 changes: 37 additions & 0 deletions
37
compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none.rs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,37 @@ | ||
| use crate::spec::{ | ||
| Arch, Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, SanitizerSet, StackProbeType, Target, | ||
| TargetMetadata, TargetOptions, | ||
| }; | ||
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| pub(crate) fn target() -> Target { | ||
| let opts = TargetOptions { | ||
| // based off the aarch64-unknown-none target at time of addition | ||
| linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), | ||
| linker: Some("rust-lld".into()), | ||
| supported_sanitizers: SanitizerSet::KCFI | SanitizerSet::KERNELADDRESS, | ||
| relocation_model: RelocModel::Static, | ||
| disable_redzone: true, | ||
| max_atomic_width: Some(128), | ||
| stack_probes: StackProbeType::Inline, | ||
| panic_strategy: PanicStrategy::Abort, | ||
| default_uwtable: true, | ||
|
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| // deviations from aarch64-unknown-none: `+v8a` -> `+v8r`; `+v8r` implies `+neon` | ||
| features: "+v8r,+strict-align".into(), | ||
| ..Default::default() | ||
| }; | ||
| Target { | ||
| llvm_target: "aarch64-unknown-none".into(), | ||
| metadata: TargetMetadata { | ||
| description: Some("Bare Armv8-R AArch64, hardfloat".into()), | ||
| tier: Some(3), | ||
| host_tools: Some(false), | ||
| std: Some(false), | ||
| }, | ||
| pointer_width: 64, | ||
| // $ clang-21 -S -emit-llvm -target aarch64 -mcpu=cortex-r82 stub.c | ||
| data_layout: "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32".into(), | ||
| arch: Arch::AArch64, | ||
| options: opts, | ||
| } | ||
| } | ||
36 changes: 36 additions & 0 deletions
36
compiler/rustc_target/src/spec/targets/aarch64v8r_unknown_none_softfloat.rs
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,36 @@ | ||
| use crate::spec::{ | ||
| Abi, Arch, Cc, LinkerFlavor, Lld, PanicStrategy, RelocModel, SanitizerSet, StackProbeType, | ||
| Target, TargetMetadata, TargetOptions, | ||
| }; | ||
|
|
||
| pub(crate) fn target() -> Target { | ||
| let opts = TargetOptions { | ||
| abi: Abi::SoftFloat, | ||
| linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes), | ||
| linker: Some("rust-lld".into()), | ||
| relocation_model: RelocModel::Static, | ||
| disable_redzone: true, | ||
| max_atomic_width: Some(128), | ||
| supported_sanitizers: SanitizerSet::KCFI | SanitizerSet::KERNELADDRESS, | ||
| stack_probes: StackProbeType::Inline, | ||
| panic_strategy: PanicStrategy::Abort, | ||
| default_uwtable: true, | ||
|
|
||
| // deviations from aarch64-unknown-none: `+v8a` -> `+v8r` | ||
| features: "+v8r,+strict-align,-neon".into(), | ||
| ..Default::default() | ||
| }; | ||
| Target { | ||
| llvm_target: "aarch64-unknown-none".into(), | ||
| metadata: TargetMetadata { | ||
| description: Some("Bare Armv8-R AArch64, softfloat".into()), | ||
| tier: Some(3), | ||
| host_tools: Some(false), | ||
| std: Some(false), | ||
| }, | ||
| pointer_width: 64, | ||
| data_layout: "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32".into(), | ||
| arch: Arch::AArch64, | ||
| options: opts, | ||
| } | ||
| } |
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84 changes: 84 additions & 0 deletions
84
src/doc/rustc/src/platform-support/aarch64v8r-unknown-none.md
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,84 @@ | ||
| # `aarch64v8r-unknown-none` and `aarch64v8r-unknown-none-softfloat` | ||
|
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| * **Tier: 3** | ||
| * **Library Support:** core and alloc (bare-metal, `#![no_std]`) | ||
|
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| Bare-metal target for CPUs in the Armv8-R architecture family, running in | ||
| AArch64 mode. Processors in this family include the | ||
| [Arm Cortex-R82][cortex-r82]. | ||
|
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||
| For Armv8-R CPUs running in AArch32 mode (such as the Arm Cortex-R52), see | ||
| [`armv8r-none-eabihf`](armv8r-none-eabihf.md) instead. | ||
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| [cortex-r82]: https://developer.arm.com/processors/Cortex-R82 | ||
|
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| ## Target maintainers | ||
|
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||
| - [Rust Embedded Devices Working Group Arm Team] | ||
| - [@rust-lang/arm-maintainers][arm_maintainers] ([rust@arm.com][arm_email]) | ||
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| [Rust Embedded Devices Working Group Arm Team]: https://github.com/rust-embedded/wg?tab=readme-ov-file#the-arm-team | ||
| [arm_maintainers]: https://github.com/rust-lang/team/blob/master/teams/arm-maintainers.toml | ||
| [arm_email]: mailto:rust@arm.com | ||
|
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||
| ## Target CPU and Target Feature options | ||
|
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| Unlike AArch64 v8-A processors, not all AArch64 v8-R processors include an FPU | ||
| (that is, not all Armv8-R AArch64 processors implement the optional Armv8 | ||
| `FEAT_FP` extension). If you do not have an FPU, or have an FPU but wish to use | ||
| a soft-float ABI anyway, you should use the `aarch64v8r-unknown-none-softfloat` | ||
| target. If you wish to use the standard hard-float Arm AArch64 calling | ||
| convention, and you have an FPU, you can use the `aarch64v8r-unknown-none` | ||
| target. | ||
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| When using the `aarch64v8r-unknown-none` target, the minimum floating-point | ||
| features assumed are the Advanced SIMD features (`FEAT_AdvSIMD`, or `+neon`), | ||
| the implementation of which is branded Arm NEON. | ||
|
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||
| If your processor supports a different set of floating-point features than the | ||
| default expectations then these should also be enabled or disabled as needed | ||
| with [`-C target-feature=(+/-)`][target-feature]. However, note that currently | ||
| Rust does not support building hard-float AArch64 targets with Advanced SIMD | ||
| support disabled. It is also possible to tell Rust (or LLVM) that you have a | ||
| specific model of Arm processor, using the [`-Ctarget-cpu`][target-cpu] option. | ||
| Doing so may change the default set of target-features enabled. | ||
|
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||
| [target-feature]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-feature | ||
| [target-cpu]: https://doc.rust-lang.org/rustc/codegen-options/index.html#target-cpu | ||
|
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| ## Requirements | ||
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| These targets are cross-compiled and use static linking. | ||
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| By default, the `lld` linker included with Rust will be used; however, you may | ||
| want to use the GNU linker instead. This can be obtained for Windows/Mac/Linux | ||
| from the [Arm Developer Website][arm-gnu-toolchain], or possibly from your OS's | ||
| package manager. To use it, add the following to your `.cargo/config.toml`: | ||
|
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| ```toml | ||
| [target.aarch64-unknown-none] | ||
| linker = "aarch64-none-elf-ld" | ||
| ``` | ||
|
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| The GNU linker can also be used by specifying `aarch64-none-elf-gcc` as the | ||
| linker. This is needed when using GCC's link time optimization. | ||
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| These targets don't provide a linker script, so you'll need to bring your own | ||
| according to the specific device you are using. Pass | ||
| `-Clink-arg=-Tyour_script.ld` as a rustc argument to make the linker use | ||
| `your_script.ld` during linking. | ||
|
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| [arm-gnu-toolchain]: https://developer.arm.com/Tools%20and%20Software/GNU%20Toolchain | ||
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| ## Cross-compilation toolchains and C code | ||
|
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| This target supports C code compiled with the `aarch64-none-elf` target | ||
| triple and a suitable `-march` or `-mcpu` flag. | ||
|
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| ## Start-up and Low-Level Code | ||
|
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| The [Rust Embedded Devices Working Group Arm Team] maintain the | ||
| [`aarch64-cpu`] crate, which may be useful for writing bare-metal code using | ||
| this target. | ||
|
|
||
| [`aarch64-cpu`]: https://docs.rs/aarch64-cpu |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,45 @@ | ||
| //@ add-minicore | ||
| //@ compile-flags: --target aarch64v8r-unknown-none-softfloat -Zmerge-functions=disabled | ||
| //@ needs-llvm-components: aarch64 | ||
| #![crate_type = "lib"] | ||
| #![feature(no_core, lang_items)] | ||
| #![no_core] | ||
|
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| extern crate minicore; | ||
| use minicore::*; | ||
|
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| // CHECK: i64 @pass_f64_C(i64 {{[^,]*}}) | ||
| #[no_mangle] | ||
| extern "C" fn pass_f64_C(x: f64) -> f64 { | ||
| x | ||
| } | ||
|
|
||
| // CHECK: i64 @pass_f32_pair_C(i64 {{[^,]*}}) | ||
| #[no_mangle] | ||
| extern "C" fn pass_f32_pair_C(x: (f32, f32)) -> (f32, f32) { | ||
| x | ||
| } | ||
|
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| // CHECK: [2 x i64] @pass_f64_pair_C([2 x i64] {{[^,]*}}) | ||
| #[no_mangle] | ||
| extern "C" fn pass_f64_pair_C(x: (f64, f64)) -> (f64, f64) { | ||
| x | ||
| } | ||
|
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||
| // CHECK: i64 @pass_f64_Rust(i64 {{[^,]*}}) | ||
| #[no_mangle] | ||
| fn pass_f64_Rust(x: f64) -> f64 { | ||
| x | ||
| } | ||
|
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| // CHECK: i64 @pass_f32_pair_Rust(i64 {{[^,]*}}) | ||
| #[no_mangle] | ||
| fn pass_f32_pair_Rust(x: (f32, f32)) -> (f32, f32) { | ||
| x | ||
| } | ||
|
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| // CHECK: void @pass_f64_pair_Rust(ptr {{.*}}%{{[^ ]+}}, ptr {{.*}}%{{[^ ]+}}) | ||
| #[no_mangle] | ||
| fn pass_f64_pair_Rust(x: (f64, f64)) -> (f64, f64) { | ||
| x | ||
| } |
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4 changes: 3 additions & 1 deletion
4
tests/codegen-llvm/sanitizer/kcfi/add-cfi-normalize-integers-flag.rs
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4 changes: 3 additions & 1 deletion
4
tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-attr-sanitize-off.rs
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4 changes: 3 additions & 1 deletion
4
tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-generalized.rs
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4 changes: 3 additions & 1 deletion
4
...en-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized-generalized.rs
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4
tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi-normalized.rs
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4 changes: 3 additions & 1 deletion
4
tests/codegen-llvm/sanitizer/kcfi/emit-kcfi-operand-bundle-itanium-cxx-abi.rs
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Given the discussion around #149622, I wonder if these targets should be added with
since the consensus seemed to be that it would make sense for our existing aarch64 targets to be configured that way except it could break people already using the targets.
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We tried that and things broke (IIRC), so we wanted to (or you to) fix all the breakages in the existing target before we flipped that switch.
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On this specfic point, as far as I could test the patch in #149622 breaks existing
aarch64-unknown-nonecode that uses theaarch64-rtand/or thesemihostingcrate. This can be observed in this example: QEMU hangs and no output is printed; but the behavior can be observed in simpler programs as well.As the AArch64 v8-R ISA builds on top of the Armv8.4-A ISA taking that patch has the same effect on this target.
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I don't currently have cycles to drive that work so I don't want to block this on it.