Link RMW to non-zero byte enable conditions.

[yvantor]

It might happen (especially with HWPEs driving part of the byte enable to zero) that sometimes a write happens with be_i = '0 but with a non-zero data on the wdata_i bus. In this particular case, the RMW FSM in the ecc_bank will still detect a RMW case, leading to either write of unproer data into the TCDM, or to deadlock conditions. This PR introduces a new signal that makes the write enable bus asserted only if the be_i is not all zero during a write operation, and use this to decide if we need to make a RMW or not.
Also, the ecc_error was not driven in the gen_ecc_input case making the {single/multi}_error_o go to x quite often.

[yvantor]

This is linked to HCI #58, but I believe making a dedicated check into the RMW logic in the ecc_sram still makes sense.

[micprog]

LGTM, thanks!