Support for multiple dbus filters and artificial cache delay#13
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martonbognar merged 7 commits intoproteus-core:mainfrom Jan 7, 2026
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This enables multiple cache levels.
Technicaly can also be zero for single-level caches, but this introduces combinatorial loops with multi-level caches
martonbognar
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Thanks for the changes! I left two comments in a review.
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This PR adds support for multiple dbus filters, e.g., to support multi-level cache hierarchies. The dbus filters are connected in the order they were added going from internal to external dbus. It adds intermediate dbusses where necessary to connect the respective filters.
It also implements an (optional) artificial cache delay to simulate cache latency. By default, the latency is set to 1 cycle. Note that with multi-level caches the latency cannot be zero as that would create combinatorial loops.