ISRO SPARC V8 Simulator

Cycle-accurate SPARC V8 simulator for UT699/LEON3FT and GR740 space processors.

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Quick Start

Docker (Recommended)

git clone https://github.com/ppraval/isro_simulator.git
cd isro_simulator
docker build -t isro-sparc-simulator:ubuntu24 .
docker run -it --name isro_sparc_sim -v $(pwd):/simulator isro-sparc-simulator:ubuntu24
./rebuild-sparc.sh

Native Linux

sudo apt-get install -y build-essential gcc-multilib qemu-user qemu-system-sparc gcc-sparc64-linux-gnu
./rebuild-sparc.sh

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Compiling SPARC Programs

# Basic compilation (32-bit static)
sparc64-linux-gnu-gcc -m32 -static -o program.elf program.c

# With optimization
sparc64-linux-gnu-gcc -m32 -static -O2 -o program.elf program.c

# With debugging symbols
sparc64-linux-gnu-gcc -m32 -static -g -o program.elf program.c

# Strict SPARC V8
sparc64-linux-gnu-gcc -m32 -static -mcpu=v8 -o program.elf program.c

# Multiple source files
sparc64-linux-gnu-gcc -m32 -static -o program.elf main.c utils.c

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Running the Simulator

Basic Execution

./sim-inorder program.elf
./sim-inorder program.elf arg1 arg2

Debugging (SDB)

./sim-inorder -debug program.elf

SDB Commands:

step / s          - Single-step one instruction
run / r           - Continue execution
break <addr>      - Set breakpoint at address
watch <addr>      - Set memory watchpoint
regs              - Display all registers
reg <name>        - Display specific register
mem <addr> <len>  - Display memory contents
disasm <addr>     - Disassemble at address
bt                - Show backtrace
quit / q          - Exit debugger

Profiling

# All profiling modes
./sim-inorder -profile:all -profile:output profile.txt program.elf

# Specific profiling
./sim-inorder -profile:inst program.elf          # Instruction counts
./sim-inorder -profile:cycle program.elf         # Cycle counts
./sim-inorder -profile:func program.elf          # Function profiling
./sim-inorder -profile:mem program.elf           # Memory access
./sim-inorder -profile:branch program.elf        # Branch statistics
./sim-inorder -profile:callgraph program.elf     # Call graph

Cache Configuration

# L1 Data Cache: 128 sets, 32B blocks, 4-way, LRU
./sim-inorder -cache:dl1 dl1:128:32:4:l program.elf

# L1 Instruction Cache: 512 sets, 32B blocks, 1-way
./sim-inorder -cache:il1 il1:512:32:1:l program.elf

# L2 Unified Cache: 1024 sets, 64B blocks, 4-way
./sim-inorder -cache:dl2 ul2:1024:64:4:l program.elf

# TLB Configuration
./sim-inorder -tlb:itlb itlb:16:4096:4:l -tlb:dtlb dtlb:32:4096:4:l program.elf

Multi-Core Simulation

./sim-inorder -instances 4 program.elf
./sim-inorder -instances 4 -shm:enable program.elf

Interrupt Simulation

./sim-inorder -interrupt:enable program.elf
./sim-inorder -interrupt:timer 1000 program.elf   # Timer every 1000 cycles

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Verifying with QEMU

# Run with QEMU
qemu-sparc32plus program.elf

# Trace system calls
qemu-sparc32plus -strace program.elf

# Log instructions
qemu-sparc32plus -d in_asm -D trace.log program.elf

# Full trace
qemu-sparc32plus -d cpu,in_asm,int -D full_trace.log program.elf

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Analyzing Binaries

# Disassemble
sparc64-linux-gnu-objdump -d program.elf

# With source (requires -g)
sparc64-linux-gnu-objdump -S program.elf

# ELF headers
sparc64-linux-gnu-readelf -a program.elf

# Symbol table
sparc64-linux-gnu-nm program.elf

# Section sizes
sparc64-linux-gnu-size program.elf

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Documentation

See Documentation/README.md for detailed guides:

• ISA Implementation
• 7-Stage Pipeline
• Cache Simulation
• Debugger (SDB)
• Profiler
• Multi-Instance
• Shared Memory
• I/O Plugins

Full getting started guide: Getting_Started.md

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Repository

• GitHub: https://github.com/ppraval/isro_simulator
• Branch: working_sim