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Front Panel Signals

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S. V. Paulauskas edited this page Sep 7, 2016 · 4 revisions

#Front Panel Test Pins Front Panel Pins

#TrigConfig0 Bit 15 of TrigConfig0 controls output of signals to the front panel of the module. TrigConfig 0 Bit 15

#TrigConfig3 Bit 31 of TrigConfig3 controls the signals output to the front panel of the module. TrigConfig3 Bit 31 ##Definitions of Signals ###Bit Set to 0

  • FTRIG_DELAY - The delayed local fast trigger for channel 0
  • FTRIG_VAL - Validated, delayed local fast trigger of channel 0
  • GLBETRIG_CE - Stretched external global validation trigger of channel 0
  • CHANETRIG_CE - Stretched channel validation trigger (i.e. parwise coincidence trigger) of channel 0
  • VANDLE_PWA[0] - The VANDLE pairwise coincidence for channel 0/1
  • GLOBAL_TRIG - The global validation trigger

###Bit Set to 1

  • FT[0] - Fast trigger for channel 0
  • FT[1] - Fast trigger for channel 1
  • FT[2] - Fast trigger for channel 2
  • VANDLE_PWA_OR - - Crate level OR of VANDLE pairwise coincidence triggers
  • BETA_PWA_TRIG_OR - - OR of Beta pairwise coincidence triggers
  • BETA_VALIDATION_TRIG - - Validation trigger of all Beta triggers

#Sample Output from Front Panel ##Simple Setup It shows a sample timing diagram of an event validated by validation triggers, including both the global validation trigger and channel coincidence trigger. This event’s local fast trigger (signal #2) was validated by the presence of both validation triggers (signal #4 and signal D0), as shown by the signal #3, i.e. the validated local fast trigger. Signal D1 shows the VANDLE pairwise coincidence trigger, whereas signal D2 shows the global validation trigger. Note: Signal #3 is only present when a data run is in progress.

Simple Pulser Setup

##VANDLE Setup VANDLE Setup

Pixie Acquisition and Analysis Software Suite

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