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Working from home
  • Kyoto University
  • 13:15 (UTC +09:00)

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nk12U/README.md

Hi there ๐Ÿ‘‹

  • Interests

    • Computer Architecture
    • FPGA
    • Integrated Circuit
    • Neural Network
    • Hardware Accelerator
  • Skills

    • C
    • Python
    • Verilog HDL
    • VHDL
    • Cadense Virtuoso
    • SPICE

Top Langs

Pinned Loading

  1. 2-Stage-Pipeline-4bit-CPU 2-Stage-Pipeline-4bit-CPU Public

    2 Stage Pipeline 4bit CPU

    Verilog 2

  2. 6-Layer-Neural-Network 6-Layer-Neural-Network Public

    6 Layer Fully Connected Neural Network classifies MNIST dataset.

    C 1

  3. Sobel-Filter-FPGA Sobel-Filter-FPGA Public

    FPGA-based Sobel Filter Edge Detection

    Verilog 2

  4. FPGA-4bit-counter FPGA-4bit-counter Public

    FPGA 4bit {up, down, johnson, graycode} counter implementation

    Verilog

  5. MNIST-classification-web-app MNIST-classification-web-app Public

    This project implements web application of MNIST classification.

    JavaScript