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Update SPIR-V submodules #8092

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Merged
s-perron merged 2 commits into from
Jan 23, 2026
+12 −12
Merged

Update SPIR-V submodules #8092

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ab072d5
prepare release
Keenuts Jan 22, 2026
8ddf426
update tests
Keenuts Jan 23, 2026
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2 changes: 1 addition & 1 deletion external/SPIRV-Headers
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Submodule SPIRV-Headers updated 12 files
+9 −9 .github/workflows/presubmit.yml
+4 −2 include/spirv/spir-v.xml
+20 −0 include/spirv/unified1/spirv.bf
+164 −32 include/spirv/unified1/spirv.core.grammar.json
+20 −0 include/spirv/unified1/spirv.cs
+46 −7 include/spirv/unified1/spirv.h
+46 −7 include/spirv/unified1/spirv.hpp
+46 −7 include/spirv/unified1/spirv.hpp11
+20 −0 include/spirv/unified1/spirv.json
+20 −0 include/spirv/unified1/spirv.lua
+20 −0 include/spirv/unified1/spirv.py
+20 −0 include/spirv/unified1/spv.d
2 changes: 1 addition & 1 deletion external/SPIRV-Tools
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Submodule SPIRV-Tools updated 102 files
16 changes: 8 additions & 8 deletions tools/clang/test/CodeGenSPIRV/intrinsics.sm6_5.multiprefix.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

// CHECK-ERROR: error: Vulkan 1.1 is required for Wave Operation but not permitted to use

// CHECK: OpCapability GroupNonUniformPartitionedNV
// CHECK: OpCapability GroupNonUniformPartitionedEXT
// CHECK: OpExtension "SPV_NV_shader_subgroup_partitioned"

StructuredBuffer<uint4> g_mask;
Expand All @@ -13,37 +13,37 @@ uint4 main(int4 input0 : ATTR0, uint4 input1 : ATTR1) : SV_Target {

// CHECK: [[input0:%[0-9]+]] = OpLoad %v4int %input0
// CHECK: [[mask:%[0-9]+]] = OpLoad %v4uint %mask
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIMul %v4int %uint_3 PartitionedExclusiveScanNV [[input0]] [[mask]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIMul %v4int %uint_3 PartitionedExclusiveScanEXT [[input0]] [[mask]]
int4 res = WaveMultiPrefixProduct(input0, mask);

// CHECK: [[input1:%[0-9]+]] = OpLoad %v4uint %input1
// CHECK: [[mask:%[0-9]+]] = OpLoad %v4uint %mask
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIMul %v4uint %uint_3 PartitionedExclusiveScanNV [[input1]] [[mask]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIMul %v4uint %uint_3 PartitionedExclusiveScanEXT [[input1]] [[mask]]
res += WaveMultiPrefixProduct(input1, mask);

// CHECK: [[input0:%[0-9]+]] = OpLoad %v4int %input0
// CHECK: [[mask:%[0-9]+]] = OpLoad %v4uint %mask
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIAdd %v4int %uint_3 PartitionedExclusiveScanNV [[input0]] [[mask]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIAdd %v4int %uint_3 PartitionedExclusiveScanEXT [[input0]] [[mask]]
res += WaveMultiPrefixSum(input0, mask);

// CHECK: [[input1:%[0-9]+]] = OpLoad %v4uint %input1
// CHECK: [[mask:%[0-9]+]] = OpLoad %v4uint %mask
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIAdd %v4uint %uint_3 PartitionedExclusiveScanNV [[input1]] [[mask]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformIAdd %v4uint %uint_3 PartitionedExclusiveScanEXT [[input1]] [[mask]]
res += WaveMultiPrefixSum(input1, mask);

// CHECK: [[input1:%[0-9]+]] = OpLoad %v4uint %input1
// CHECK: [[mask:%[0-9]+]] = OpLoad %v4uint %mask
// CHECK: {{%[0-9]+}} = OpGroupNonUniformBitwiseAnd %v4uint %uint_3 PartitionedExclusiveScanNV [[input1]] [[mask]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformBitwiseAnd %v4uint %uint_3 PartitionedExclusiveScanEXT [[input1]] [[mask]]
res += WaveMultiPrefixBitAnd(input1, mask);

// CHECK: [[input1:%[0-9]+]] = OpLoad %v4uint %input1
// CHECK: [[mask:%[0-9]+]] = OpLoad %v4uint %mask
// CHECK: {{%[0-9]+}} = OpGroupNonUniformBitwiseOr %v4uint %uint_3 PartitionedExclusiveScanNV [[input1]] [[mask]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformBitwiseOr %v4uint %uint_3 PartitionedExclusiveScanEXT [[input1]] [[mask]]
res += WaveMultiPrefixBitOr(input1, mask);

// CHECK: [[input1:%[0-9]+]] = OpLoad %v4uint %input1
// CHECK: [[mask:%[0-9]+]] = OpLoad %v4uint %mask
// CHECK: {{%[0-9]+}} = OpGroupNonUniformBitwiseXor %v4uint %uint_3 PartitionedExclusiveScanNV [[input1]] [[mask]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformBitwiseXor %v4uint %uint_3 PartitionedExclusiveScanEXT [[input1]] [[mask]]
res += WaveMultiPrefixBitXor(input1, mask);
return res;
}
4 changes: 2 additions & 2 deletions tools/clang/test/CodeGenSPIRV/sm6_5.wave-match.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,12 @@

// CHECK-ERROR: error: Vulkan 1.1 is required for Wave Operation but not permitted to use

// CHECK: OpCapability GroupNonUniformPartitionedNV
// CHECK: OpCapability GroupNonUniformPartitionedEXT
// CHECK: OpExtension "SPV_NV_shader_subgroup_partitioned"

uint4 main(uint4 input : ATTR0) : SV_Target {
// CHECK: [[input:%[0-9]+]] = OpLoad %v4uint %input
// CHECK: {{%[0-9]+}} = OpGroupNonUniformPartitionNV %v4uint [[input]]
// CHECK: {{%[0-9]+}} = OpGroupNonUniformPartitionEXT %v4uint [[input]]
uint4 res = WaveMatch(input);
return res;
}
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