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2 changes: 0 additions & 2 deletions examples/xegpu_matmul/matmul.py
Original file line number Diff line number Diff line change
Expand Up @@ -324,8 +324,6 @@ def parse_cli():
"bufferized",
"xegpu-initial",
"xegpu-wg",
"xegpu-sg",
"xegpu-inst",
"final",
],
help="Dump kernel IR at different stages of lowering.",
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7 changes: 1 addition & 6 deletions examples/xegpu_matmul/schedule.py
Original file line number Diff line number Diff line change
Expand Up @@ -381,12 +381,7 @@ def convert_layout(value, input, target):

def bundle_xegpu_to_binary(mod, stop_at_stage: str = "") -> ir.Module:
"""Schedule for lowering xegpu wg level to binary."""
# This schedule corresponds to upstream MLIR XeVM lowering pipeline
# and is payload independent.

# This pipeline causes performance regression with the existing
# xegpu transform ops.
# FIXME Use anchor layouts in transform ops.
# upstream xegpu/xevm pipeline is payload independent.
mod = apply_registered_pass(
mod, "gpu-lower-to-xevm-pipeline", options={"xegpu-op-level": "workgroup"}
)
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