dma: Add dw_axi dma driver for ISH 5.8.0 #71
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Pull request overview
This PR adds support for the DW AXI DMA driver for Intel ISH version 5.8.0, introducing a new DMA IP architecture. The implementation includes hardware register definitions, channel management infrastructure, and conditional build logic to select between the legacy ANN 1.0 DMA driver (for ISH 5.4.1/5.6.0) and the new DW AXI driver (for ISH 5.8.0+).
Key changes:
- Added comprehensive register definitions for the DW AXI DMA controller and miscellaneous registers
- Implemented core DMA driver with support for memory-to-memory and peripheral transfers
- Added conditional compilation in CMake to select appropriate driver based on SoC version
Reviewed changes
Copilot reviewed 6 out of 7 changed files in this pull request and generated 5 comments.
Show a summary per file
| File | Description |
|---|---|
| zephyr/drivers/dma/CMakeLists.txt | Adds conditional compilation to select between legacy ANN 1.0 and new DW AXI DMA drivers based on ISH SoC version |
| bsp_sedi/soc/intel_ish/include/sedi_soc_regs.h | Defines DMA channel and miscellaneous register offset constants |
| bsp_sedi/soc/intel_ish/include/sedi_soc_defs.h | Removes unused DMA_MISC_FUNC constant |
| bsp_sedi/soc/common/include/sedi_dmac_regs.h | Auto-generated register definitions for DW AXI DMA controller common registers |
| bsp_sedi/soc/common/include/sedi_dma_misc_regs.h | Auto-generated register definitions for DMA miscellaneous control registers |
| bsp_sedi/drivers/dma/sedi_dma_dw_axi.c | Complete DW AXI DMA driver implementation with channel control, transfer operations, and interrupt handling |
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It's a new DMA IP used for ISH since ISH 5.8.0. The source file is a copy of ISH code base. Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Have its function enabled always. Signed-off-by: Dong Wang <dong.d.wang@intel.com>
- Fix direction checks: use logical OR (||) instead of bitwise OR (|) when testing config->direction. - Remove unreachable return in cal_block_ts(). - Use bitwise OR (|) when composing CHENREG write mask instead of '+': addition can produce incorrect results if bits overlap; | correctly sets the intended bit flags. Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Run clang-format on it and make it pass checkpatch checking. Signed-off-by: Dong Wang <dong.d.wang@intel.com>
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Pull request overview
Copilot reviewed 6 out of 7 changed files in this pull request and generated no new comments.
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Checkpatch reports spelling error on them. Those are defined in ISH old OSXML files and not in LNL PV version. And currently they're not used by DMA driver. Signed-off-by: Dong Wang <dong.d.wang@intel.com>
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Dec 25, 2025
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It's a new DMA IP used for ISH since ISH 5.8.0.