[WIP] Group LRAM timings by cell configuration

[mkurc-ant]

The LRAM clock-to-q timings seem pretty high (~10ns) as the datasheet says that the worst case fmax is around 130MHz.

To investigate this I isolated LRAM fuzzing to a separate fuzzer, added randomizing output register enabling and added grouping of fuzzed timings by cell types and their configurations.

This is a work in progress, currently I get the following results for the grouping:

LRAM timing groups (CLK -> DOA|DOB) speed 10:
DPC512K
 ('NO_REG', 'CLK_to_DOA') {((13880, 14646), (13880, 14646))}
 ('NO_REG', 'CLK_to_DOB') {((13979, 14732), (13979, 14732)), ((1145, 2022), (1145, 2022))}
 ('OUT_REG', 'CLK_to_DOA') {((1099, 1994), (1099, 1994))}
 ('OUT_REG', 'CLK_to_DOB') {((13979, 14732), (13979, 14732)), ((1145, 2022), (1145, 2022))}
PDPSC512K
 ('OUT_REG', 'CLK_to_DOB') {((1145, 2022), (1145, 2022))}
 ('NO_REG', 'CLK_to_DOB') {((13979, 14732), (13979, 14732))}
SP512K
 ('OUT_REG', 'CLK_to_DOA') {((1096, 1995), (1096, 1995))}
 ('NO_REG', 'CLK_to_DOA') {((9019, 9788), (9019, 9788))}

For some combinations there are two timing sets while there should be only one.

[gatecat]

this del of both params seems kind of suspicious to me

[gatecat]

no worries if you've been busy but I'm wondering if the force-push fixed things at all?

[mkurc-ant]

Hi, I'll do the rebase once I carve some time.