Welcome!

HEEPidermis is a chip based on the open-source RISC-V platform X-HEEP intended to record Galvanic Skin Response (GSR) and Impedance (Z). HEEPidermis is capable of injecting arbitrary-wave currents on the skin with an 8-bit iDAC and measure voltage through a 14-bit VCO-based ADC. Parameters of the iDAC and ADC can be programmed dynamically using the on-board Ibex CPU. Acquired data can be stored in the 16 kB RAM memory for on-chip processing, compression, and transmission.

HEEPidermis can be interfaced through JTAG for code-debugging, SPI to obtain recordings from memory, or UART. External ADCs and peripherals can also be commanded via SPI.

The Direct Memory Access (DMA) block allows the chip to operate autonomously without the constant interaction of the CPU. Given proper configuration, the DMA can take care of controlling the current injection profile, read data from the local ADC (or an external one), store data and/or transmit it through SPI. The DMA can additionally re-direct data to a digital Level Crossing (dLC) block to filter data and reduce the output data rate. The output of the dLC can be stored in memory (along timestamps) or be exposed to be used as feedback loop for the analog front-end, interface with transmission circuits or as input to Spiking Neural Networks. The dLC block also accepts inputs from analog LC ADCs (instead of the on-chip ADC).

HEEPidermis can also decimate 1-bit ΔΣ-ADCs' output with an integrated CIC filter or, alternatively, with an integrated custom smoothing stage, followed by the dLC block.

Being based on the X-HEEP platform, you can check its documentation on how to program, debug, or understand how it was built. We suggest using the vendorized X-HEEP's documentation. For all HEEPidermis-specific documentation, please refer to the documentation below.

   

Index

• Analog Front End

  • Analog subsystem
  • iDAC
  • VCO

• Digital Back End

  • CPU
  • DMA (how we use it)
  • DMA
  • SPI host
  • SPI slave
  • digital Level-Crossing
  • ΔΣ decimation (CIC filter)
  • ΔΣ decimation (SES filter)

• Related documents

  • HEEPidermis
  • ΔΣ Decimation theory
  • iDAC precursor
  • VCO Design

Prerequisites

Since this project is based on X-HEEP, it has the same prerequisites.

1. Follow X-HEEP's Prerequisite section to download the necessary tools. To correctly generate hardware and software, an extended version of the core-v-mini-mcu environment is required. To install it run:

   make conda

Make sure the Conda environment is active:

conda activate heepidermis

2. Make sure that the following tools are available in your system's PATH:
   • To compile code: RISC-V toolchain version 2022.01.17, supporting at least rv32imc. Newer versions will work but compilation will have a bug when reporting memory usage.
   • To format SystemVerilog (in case you want to open a PR): Verible version 0.0-4023-gc1271a00
   • To simulate (open source): Verilator 4.210
   • To see waveforms out of Verilator: GTKWave
   • In case you have the licences:
     • Siemens QuestaSim version 2020.4 or above
     • Synopsys Design Compiler version 2020.09 or above

You can follow the instructions on how to install these tools on the X-HEEP documentation - Manual setup.

Programming the ASIC

You can program the ASIC through 3 alternatives:

• JTAG
• Loading an external flash that HEEPidermis can read through SPI
• Loading the program in RAM through the SPI slave peripheral

Programming through JTAG

You need to connect the JTAG interface to an FTDI chip. This is avaialble on the EPFL programmer or on the CHEEP boards (currently only available upon request).

1. The BOOT switches should be set to

Signal	Value
FLASH_EXEC	0
BOOT_SEL	0

2. Set the system clock to 1 MHz. You can do that in two steps if you have the CHEEP board, and have exported the variable $CHEEP_BOARDS pointing to the folder where the repo is.

make board_config
make board_freq PLL_FREQ=1_000_000  #default

3. Compile the code

make app BOOT_MODE=jtag

4. Open openOCD and picocom to see the UART output

make jtag_open

5. Open GDB and run the program

make jtag_run

Useful commands:

c (continue)

monitor reset hart

monitor pc _start

si (next instruction)

disassembler

x/8i (see the following instructions).

6. Exit GDB with ctrl+C and type quit
7. Close the openOCD and uart terminals with

make jtag_close

Programming from the FLASH

Testing...

Programming through SPI

Testing...

RTL Simulation

The included makefile proves all the necessary rules to build HEEPidermis:

1. Generate all the RTL files (and software headers):

   make cheep-gen

   Some X-HEEP configuration parameters (e.g. BUS, MEMORY_BANKS etc.) are still supported, although the default configuration may differ (check peripherals_config). In general, these should not be passed through the makefile targets but should be configured in the hjson files in the config folder.

2. Build the simulation model:

   make verilator-build     # Verilator
   make questasim-build     # QuestaSim

3. The software build process is primarily handled by X-HEEP, and most of its example applications will work on HEEPidermis as well. You can choose other BOOT_MODE, just be sure to match it with the one used with make *-build (by default they use fore). force will be the faster for simulation.

make app PROJECT=test_dlc_vco BOOT_MODE=force

The combinations of compatible linker and boot modes can be found here:

1. Launch the simulation with the compiled firmware:

   make verilator-run       # Verilator with waveforms dump
   make verilator-opt       # Verilator without waveforms dump
   make questasim-run       # QuestaSim
   make questasim-gui       # QuestaSim with GUI

   You can also set other parameters like the FUSESOC_FLAGS, LOG_LEVEL, BOOT_MODE, VCD_MODE, etc. to customize the simulation. Refer to the makefile for more details.

2. HEEPidermis stdout is exposed through a UART DPI interface at /dev/pts/<N>, where N is a number printed on the simulation log during execution. You can connect to it using screen or similar tools, e.g.:

   screen /dev/pts/0

   The UART output is also stored to the uart.log file in the common simulation directory (build/sim-common/uart.log).

   Using printf() will significantly increase the firmware execution time and therefore the simulation. For quick debugging, it recommended to use the return value from main instead. When it is not zero, the testbench will print it out at the end of the simulation.

3. The waveforms dumped during the simulation can be opened using:

   make verilator-waves # after Verilator simulation
   make questasim-waves # after QuestaSim simulation

This will open the waveforms (example from test_dlc_vco application):

Assuming that your firmware is already available, steps 1., 3., and 4. can be repeated with a single command using the verilator-sim or questasim-sim targets.

Questions?

Have questions? curiosities? ideas on how to exploit HEEPidermis? Want to contribute on following versions of the SoC? Drop an email :) juan.sapriza@epfl.ch