The cpuid package provides a comprehensive set of functions and data structures to query detailed information about the host CPU. It supports multiple architectures and operating systems, enabling you to identify the CPU vendor, supported features, caches, TLB configurations, and more.
| Architecture | OS | Notes |
|---|---|---|
| x86 (386) | Linux, Darwin, Windows | Full CPUID instruction support |
| x86_64 (amd64) | Linux, Darwin, Windows | Full CPUID instruction support |
| ARM | Linux | MIDR-based identification |
| ARM64 | Linux | MIDR-based identification |
| ARM64 | Darwin (macOS) | Apple Silicon support via sysctl |
x86/x86_64:
- Intel (GenuineIntel)
- AMD (AuthenticAMD)
ARM/ARM64:
- ARM Ltd.
- Broadcom
- Cavium
- DEC
- NVIDIA
- APM
- Qualcomm
- Marvell
Apple Silicon:
- M1, M1 Pro, M1 Max, M1 Ultra
- M2, M2 Pro, M2 Max, M2 Ultra
- M3, M3 Pro, M3 Max, M3 Ultra
- M4, M4 Pro, M4 Max, M4 Ultra
go get github.com/earentir/cpuid- Vendor Identification - Detects CPU vendor (Intel, AMD, Apple, ARM, etc.)
- CPU Model and Family - Retrieves raw and effective CPU family, model, stepping IDs
- Brand String - Extracts the full human-readable CPU name
- Core and Thread Topology - Determines cores, threads, and topology information
- Addressing Capabilities - Physical and linear address bits
- Feature Detection - Comprehensive CPU feature flags across multiple categories
- Cache Information - Details about L1, L2, L3 caches
- TLB Details - Translation Lookaside Buffer configuration
- Intel Hybrid CPU Support - P-core and E-core detection
- Apple Silicon Support - Detailed Apple chip information including performance/efficiency cores
- Offline Mode - Analyze CPUID data from JSON files
Stores information about CPU cache levels.
type CPUCacheInfo struct {
Level uint32 // Cache level (1, 2, 3)
Type string // "Data", "Instruction", or "Unified"
SizeKB uint32 // Size in kilobytes
Ways uint32 // Associativity (ways)
LineSizeBytes uint32 // Cache line size
TotalSets uint32 // Number of sets
MaxCoresSharing uint32 // Maximum cores sharing this cache
Flags uint32 // Cache flags
SelfInitializing bool // Self-initializing cache
FullyAssociative bool // Fully associative cache
MaxProcessorIDs uint32 // Maximum processor IDs
WritePolicy string // "Write Back", "Write Through", etc.
}Stores processor model information.
type ProcessorModel struct {
SteppingID uint32 // Stepping ID
ModelID uint32 // Model ID
FamilyID uint32 // Family ID
ProcessorType uint32 // Processor type
ExtendedModelID uint32 // Extended model ID
ExtendedFamilyID uint32 // Extended family ID
ExtendedModel uint32 // Computed effective model
ExtendedFamily uint32 // Computed effective family
}Stores basic CPU information.
type ProcessorInfo struct {
MaxLogicalProcessors uint32 // Maximum logical processors
InitialAPICID uint32 // Initial APIC ID
PhysicalAddressBits uint32 // Physical address bits
LinearAddressBits uint32 // Linear address bits
CoreCount uint32 // Number of cores
ThreadPerCore uint32 // Threads per core
}Stores TLB configuration.
type TLBInfo struct {
Vendor string // CPU vendor
L1 TLBLevel // L1 TLB info
L2 TLBLevel // L2 TLB info
L3 TLBLevel // L3 TLB info
}
type TLBLevel struct {
Data []TLBEntry // Data TLB entries
Instruction []TLBEntry // Instruction TLB entries
Unified []TLBEntry // Unified TLB entries
}
type TLBEntry struct {
PageSize string // Page size (e.g., "4KB", "2MB", "1GB")
Entries int // Number of entries
Associativity string // Associativity description
}Stores Intel hybrid CPU information.
type IntelHybridInfo struct {
HybridCPU bool // Is hybrid CPU
NativeModelID uint32 // Native model ID
CoreType uint32 // Core type code
CoreTypeName string // "Performance core (P-core)" or "Efficient core (E-core)"
}Stores Apple Silicon specific information.
type AppleSiliconInfo struct {
ChipName string // e.g., "Apple M4 Pro"
Generation int // 1, 2, 3, or 4
Variant string // "Base", "Pro", "Max", or "Ultra"
PerformanceCores int // Number of P-cores
EfficiencyCores int // Number of E-cores
TotalCores int // Total cores
MemorySize int64 // Memory size in bytes
HasNeuralEngine bool // Neural Engine support
HasProResSupport bool // ProRes support
HasThunderbolt bool // Thunderbolt support
MaxMemoryBandwidth string // Memory bandwidth
}type Entry struct {
Leaf uint32 `json:"leaf"`
Subleaf uint32 `json:"subleaf"`
EAX uint32 `json:"eax"`
EBX uint32 `json:"ebx"`
ECX uint32 `json:"ecx"`
EDX uint32 `json:"edx"`
}
type Data struct {
Entries []Entry `json:"entries"`
}func GetVendorID(offline bool, filename string) stringReturns the CPU vendor ID string (e.g., "GenuineIntel", "AuthenticAMD", "Apple").
func GetVendorName(offline bool, filename string) stringReturns the human-readable vendor name (e.g., "Intel", "AMD", "Apple").
func GetBrandString(maxExtFunc uint32, offline bool, filename string) stringReturns the full CPU brand string (e.g., "Intel(R) Core(TM) i9-12900K").
func GetModelData(offline bool, filename string) ProcessorModelReturns processor model information including family, model, and stepping.
func GetMaxFunctions(offline bool, filename string) (uint32, uint32)Returns maximum supported standard and extended CPUID function values.
func GetProcessorInfo(maxFunc, maxExtFunc uint32, offline bool, filename string) ProcessorInfoReturns detailed processor information including core count and addressing capabilities.
func GotEnoughCores(coreCount uint32, realcores bool, offline bool, filename string) boolChecks if the CPU has at least the specified number of cores.
func GetCacheInfo(maxFunc, maxExtFunc uint32, vendorID string, offline bool, filename string) ([]CPUCacheInfo, error)Returns cache information for all cache levels.
func GetTLBInfo(maxFunc, maxExtFunc uint32, offline bool, filename string) (TLBInfo, error)Returns TLB configuration for L1, L2, and L3.
func GetAllFeatureCategories() []stringReturns all available feature categories.
func GetAllFeatureCategoriesDetailed() map[string][]map[string]stringReturns detailed information about all features in all categories.
func GetAllKnownFeatures(category string) []stringReturns all known features for a given category.
func GetSupportedFeatures(category string, offline bool, filename string) []stringReturns all features supported by the current CPU in a given category.
func IsFeatureSupported(featureName string, offline bool, filename string) boolChecks if a specific feature is supported.
func GetIntelHybrid(offline bool, filename string) IntelHybridInfoReturns hybrid CPU information (works for both Intel and Apple Silicon).
func GetAppleSiliconInfo() AppleSiliconInfoReturns detailed Apple Silicon information.
func GetAppleSiliconFeatures() []stringReturns all features supported by Apple Silicon.
func IsAppleSiliconFeatureSupported(feature string) boolChecks if a specific Apple Silicon feature is supported.
func CaptureData(filename string) errorCaptures all CPUID data and saves to a JSON file.
func DataFromFile(filename string) (Data, error)Loads CPUID data from a JSON file.
The package supports detection of 49+ feature categories with hundreds of individual features for Intel and AMD processors:
| Category | Description | Features |
|---|---|---|
| StandardECX | Standard Features (ECX register) | SSE3, PCLMULQDQ, MONITOR, VMX, SMX, SSSE3, FMA, SSE4.1, SSE4.2, AES, AVX, F16C, RDRAND, and more |
| StandardEDX | Standard Features (EDX register) | FPU, VME, DE, PSE, TSC, MSR, PAE, MCE, APIC, SEP, MTRR, MMX, SSE, SSE2, HTT, and more |
| ExtendedEBX | Extended Features (EBX register) | FSGSBASE, BMI1, AVX2, BMI2, ERMS, INVPCID, AVX512F, AVX512DQ, RDSEED, SHA, AVX512BW, AVX512VL, and more |
| ExtendedECX | Extended Features (ECX register) | PREFETCHWT1, AVX512_VBMI, UMIP, PKU, VAES, VPCLMULQDQ, AVX512_VNNI, LA57, RDPID, and more |
| AMDExtendedECX | AMD Extended Features | LAHF_LM, SVM, ABM, SSE4A, 3DNOWPREFETCH, IBS, XOP, FMA4, TBM, MWAITX, and more |
| PowerManagement | Power Management | DTHERM, IDA, ARAT, HWP, HDC, TURBO3, CPB, RAPL, and more |
| SGX | Software Guard Extensions | SGX1, SGX2, ENCLV, ENCLS, ENCLU, SEV, SEV_ES, SEV_SNP, and more |
| PT | Processor Trace | CR3_FILTERING, PSB, IP_FILTERING, MTC, PTWRITE, and more |
| MTRR | Memory Type Range Registers | MTRR_VCNT, MTRR_FIX, MTRR_WC, MTRR_SMRR, and more |
| CacheFeatures | Cache Properties | CACHE_SELF_SNOOP, CACHE_INCLUSIVENESS, WBINVD, and more |
| XSave | Extended State (XSAVE) | XSAVEOPT, XSAVEC, XGETBV_ECX1, XSAVES, XFD, and more |
| PerformanceMonitor | Performance Monitoring | PMC counters, PEBS, LBR, core cycles, instructions retired, and more |
| Virtualization | Virtualization | VMX, EPT, VPID, SVM, NPT, VMCB_CLEAN, and more |
| ExtendedSecurity | Security Features | SMAP, SMEP, UMIP, IBT, SHSTK, CET_IBT, SEV, SEV_SNP, and more |
| PlatformSecurity | Platform Security | TPM, SKINIT, SEV, SME, VMPL, SGX_LC, and more |
| ExtendedDebug | Debug Features | LBR, PEBS, IPT, BTS, IBS_FETCH, IBS_OP, and more |
| AdvancedMatrixExtensions | AMX Features | AMX_BF16, AMX_TILE, AMX_INT8, AMX_FP16, and more |
| SMM | System Management Mode | SMM_MONITOR, SMM_VMCALL, SMM_LOCK, SKINIT, and more |
| Real-TimeInstructions | Real-Time Instructions | HRESET, LAM, FRED, LKGS, MWAITX, MONITORX, and more |
| CoreThread | Core & Thread | APIC_IDS, CORE_COUNT, HYBRID_ARCH, CCD_ID, CCX_ID, and more |
| ErrorDetection | Error Detection | MCA, MCE, DEP, SUCCOR, SCALABLE_MCA, and more |
| Prefetch | Prefetch Features | PREFETCHW, PREFETCHWT1, 3DNOW_PREFETCH, and more |
| BUS | Bus Features | BUS_LOCK_DETECT, SPLIT_LOCK_DETECT, QOS_ENF, and more |
| ApplicationTargeted | Application Features | WAITPKG, KEYLOCKER, HFI, FAST_SHORT_REP, and more |
| Encryption | Encryption | AES_128, AES_256, VAES, SHA_1, SHA_256, SHA_512, GFNI, KL, and more |
| SpeculationControl | Speculation Control | IBRS, STIBP, SSBD, IBPB, L1D_FLUSH, MD_CLEAR, and more |
| BranchPrediction | Branch Prediction | IBC, IBPB_BRTYPE, SRSO, BHI_CTRL, BHB_CLEAR, and more |
| VectorNeuralNetwork | Neural Network | AVX512_4VNNIW, AVX512_4FMAPS, AMX_BF16, AVX_VNNI, and more |
| TransactionalSynchronization | TSX | TSX_HLE, TSX_RTM, TSX_CTRL, RTM_ALWAYS_ABORT, and more |
| NestedVirtualization | Nested Virtualization | NPT, NRIPS, VMCB_CLEAN, VGIF, VMX_EPT, SHADOW_VMCS, and more |
| MemoryBandwidth | Memory Bandwidth | RDT_M, RDT_A, MBA, CQM, L3_MONITORING, and more |
| AdvancedPowerManagement | Advanced Power | APM_CNT, WDT, HWPS, TSC_INVARIANT, CPB, RAPL, and more |
| Category | Features |
|---|---|
| ARM Standard | NEON, FP16, CRC32, AES, SHA1, SHA256, PMULL, ATOMICS, ASIMD, FCMA, JSCVT, LRCPC, DPB, DPB2, FRINTTS, SB, SSBS, BTI, FHM, DIT, FP, ASIMD_HP, ASIMD_DP, ASIMDFHM, AMX |
| M3/M4 Specific | RAYTRACING, MESH_SHADING, DYNAMIC_CACHING |
| M4 Specific | SME, SME2, SVE2, FP8 |
package main
import (
"fmt"
"github.com/earentir/cpuid"
)
func main() {
// Get vendor information
vendorID := cpuid.GetVendorID(false, "")
vendorName := cpuid.GetVendorName(false, "")
fmt.Printf("Vendor: %s (%s)\n", vendorName, vendorID)
// Get brand string
maxFunc, maxExtFunc := cpuid.GetMaxFunctions(false, "")
brand := cpuid.GetBrandString(maxExtFunc, false, "")
fmt.Printf("Brand: %s\n", brand)
// Get processor info
info := cpuid.GetProcessorInfo(maxFunc, maxExtFunc, false, "")
fmt.Printf("Cores: %d, Threads per core: %d\n", info.CoreCount, info.ThreadPerCore)
// Check feature support
if cpuid.IsFeatureSupported("AVX2", false, "") {
fmt.Println("AVX2 is supported!")
}
}caches, err := cpuid.GetCacheInfo(maxFunc, maxExtFunc, vendorID, false, "")
if err == nil {
for _, cache := range caches {
fmt.Printf("L%d %s Cache: %d KB, %d-way, %d byte line\n",
cache.Level, cache.Type, cache.SizeKB, cache.Ways, cache.LineSizeBytes)
}
}// List all categories
categories := cpuid.GetAllFeatureCategories()
for _, cat := range categories {
features := cpuid.GetSupportedFeatures(cat, false, "")
fmt.Printf("%s: %v\n", cat, features)
}// Capture current CPU data
err := cpuid.CaptureData("mycpu.json")
// Later, analyze offline
vendorID := cpuid.GetVendorID(true, "mycpu.json")
features := cpuid.GetSupportedFeatures("StandardECX", true, "mycpu.json")// On macOS with Apple Silicon
info := cpuid.GetAppleSiliconInfo()
fmt.Printf("Chip: %s (Generation %d, %s)\n", info.ChipName, info.Generation, info.Variant)
fmt.Printf("Performance Cores: %d, Efficiency Cores: %d\n",
info.PerformanceCores, info.EfficiencyCores)
features := cpuid.GetAppleSiliconFeatures()
fmt.Printf("Supported features: %v\n", features)See LICENSE file for details.