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Remove the previous magic values, and add bit macros with explicit names. This makes reading the code easier, and is more is sync with what's done for device registers.
We do not check whether the running CPU supports the CPUID instruction, but this should not be the case unless we are running on ancient hardware.
This structure contains information about the system's CPU. It is intended to be used to fetch the CPU's capabilities instead of using and parsing the CPUID instruction each time. We will surely be adding more fields in the future (e.g. processor model).
Split the mmu_init() function into distinct parts using sub-functions to make it more readable. This will also help when having to initialize the PAT table in the next commits.
Reference: Intel SDM 2023 volume 3 chapter 12 (Memory cache control)
The caching policy used for a vm_segment is now explicitely configured inside the segment's flag. The chosen policy is forwarded to the MMU API when mapping an address inside the segment. This commit also adds the vm_set_policy() function that can be called to dynamically re-configure these policies for an already existing segment. When no policies are specified the API defaults back to using write-back caching (regular caching).
Accesses to memory-mapped I/O often have side-effects and should not be combined or delayed. Add a new VM_IOMEM flag that should be used with memory-mapped registers.
d4ilyrun
added
target: kernel
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Resolves #59