build(deps): bump urllib3 from 2.0.7 to 2.2.2 in /drivers/gpu/drm/ci/xfails

arch/loongarch/Kconfig

@@ -180,6 +180,7 @@ config LOONGARCH
 	select PERF_USE_VMALLOC
 	select RTC_LIB
 	select SPARSE_IRQ
+	select SYS_SUPPORTS_HIGHMEM
 	select SYSCTL_ARCH_UNALIGN_ALLOW
 	select SYSCTL_ARCH_UNALIGN_NO_WARN
 	select SYSCTL_EXCEPTION_TRACE
@@ -224,6 +225,19 @@ config STACKTRACE_SUPPORT
 	bool
 	default y
 
+#
+# - Highmem only makes sense for the 32-bit kernel.
+# - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
+#   know they might have memory configurations that could make use of highmem
+#   support.
+#
+config HIGHMEM
+	bool "High Memory Support"
+	depends on 32BIT && CPU_SUPPORTS_HIGHMEM && SYS_SUPPORTS_HIGHMEM
+
+config SYS_SUPPORTS_HIGHMEM
+	bool
+
 # MACH_LOONGSON32 and MACH_LOONGSON64 are deliberately carried over from the
 # MIPS Loongson code, to preserve Loongson-specific code paths in drivers that
 # are shared between architectures, and specifically expecting the symbols.
@@ -696,6 +710,7 @@ config ARCH_HIBERNATION_POSSIBLE
 
 source "kernel/power/Kconfig"
 source "drivers/acpi/Kconfig"
+source "drivers/cpufreq/Kconfig"
 
 endmenu
 

arch/loongarch/Kconfig.debug

@@ -38,3 +38,9 @@ config UNWINDER_ORC
 	  by roughly 2-4MB, depending on your kernel config.
 
 endchoice
+
+config SPINLOCK_TEST
+	tristate "Enable spinlock timing tests in debugfs"
+	default n
+	help
+	  Add several files to the debugfs to test spinlock speed.

arch/loongarch/boot/dts/loongson/Makefile

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_CPU_LOONGSON64)	+= loongson3_ls7a.dtb
+
+obj-y				+= $(patsubst %.dtb, %.dtb.o, $(dtb-y))

arch/loongarch/boot/dts/loongson/loongson3.dtsi

@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: GPL-2.0
+/ {
+	/*
+	 * Loongson-3 may have as many as 4 nodes, each node has 4 cores.
+	 * Each core has its own pcache and cores in the same node share scache.
+	 */
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x0>;
+			l2-cache = <&vcache0>;
+			next-level-cache = <&scache0>;
+		};
+
+		cpu@1 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x1>;
+			l2-cache = <&vcache1>;
+			next-level-cache = <&scache0>;
+		};
+
+		cpu@2 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x2>;
+			l2-cache = <&vcache2>;
+			next-level-cache = <&scache0>;
+		};
+
+		cpu@3 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x3>;
+			l2-cache = <&vcache3>;
+			next-level-cache = <&scache0>;
+		};
+
+		cpu@4 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x4>;
+			l2-cache = <&vcache4>;
+			next-level-cache = <&scache1>;
+		};
+
+		cpu@5 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x5>;
+			l2-cache = <&vcache5>;
+			next-level-cache = <&scache1>;
+		};
+
+		cpu@6 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x6>;
+			l2-cache = <&vcache6>;
+			next-level-cache = <&scache1>;
+		};
+
+		cpu@7 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x7>;
+			l2-cache = <&vcache7>;
+			next-level-cache = <&scache1>;
+		};
+
+		cpu@8 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x8>;
+			l2-cache = <&vcache8>;
+			next-level-cache = <&scache2>;
+		};
+
+		cpu@9 {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0x9>;
+			l2-cache = <&vcache9>;
+			next-level-cache = <&scache2>;
+		};
+
+		cpu@a {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0xa>;
+			l2-cache = <&vcachea>;
+			next-level-cache = <&scache2>;
+		};
+
+		cpu@b {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0xb>;
+			l2-cache = <&vcacheb>;
+			next-level-cache = <&scache2>;
+		};
+
+		cpu@c {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0xc>;
+			l2-cache = <&vcachec>;
+			next-level-cache = <&scache3>;
+		};
+
+		cpu@d {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0xd>;
+			l2-cache = <&vcached>;
+			next-level-cache = <&scache3>;
+		};
+
+		cpu@e {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0xe>;
+			l2-cache = <&vcachee>;
+			next-level-cache = <&scache3>;
+		};
+
+		cpu@f {
+			compatible = "loongson,loongson3";
+			device_type = "cpu";
+			reg = <0xf>;
+			l2-cache = <&vcachef>;
+			next-level-cache = <&scache3>;
+		};
+
+		vcache0: l2-cache0 {
+			compatible = "cache";
+			next-level-cache = <&scache0>;
+		};
+
+		vcache1: l2-cache1 {
+			compatible = "cache";
+			next-level-cache = <&scache0>;
+		};
+
+		vcache2: l2-cache2 {
+			compatible = "cache";
+			next-level-cache = <&scache0>;
+		};
+
+		vcache3: l2-cache3 {
+			compatible = "cache";
+			next-level-cache = <&scache0>;
+		};
+
+		vcache4: l2-cache4 {
+			compatible = "cache";
+			next-level-cache = <&scache1>;
+		};
+
+		vcache5: l2-cache5 {
+			compatible = "cache";
+			next-level-cache = <&scache1>;
+		};
+
+		vcache6: l2-cache6 {
+			compatible = "cahce";
+			next-level-cache = <&scache1>;
+		};
+
+		vcache7: l2-cache7 {
+			compatible = "cache";
+			next-level-cache = <&scache1>;
+		};
+
+		vcache8: l2-cache8 {
+			compatible = "cache";
+			next-level-cache = <&scache2>;
+		};
+
+		vcache9: l2-cache9 {
+			compatible = "cache";
+			next-level-cache = <&scache2>;
+		};
+
+		vcachea: l2-cachea {
+			compatible = "cache";
+			next-level-cache = <&scache2>;
+		};
+
+		vcacheb: l2-cacheb {
+			compatible = "cache";
+			next-level-cache = <&scache2>;
+		};
+
+		vcachec: l2-cachec {
+			compatible = "cache";
+			next-level-cache = <&scache3>;
+		};
+
+		vcached: l2-cached {
+			compatible = "cache";
+			next-level-cache = <&scache3>;
+		};
+
+		vcachee: l2-cachee {
+			compatible = "cache";
+			next-level-cache = <&scache3>;
+		};
+
+		vcachef: l2-cachef {
+			compatible = "cache";
+			next-level-cache = <&scache3>;
+		};
+
+		scache0: l3-cache0 {
+			compatible = "cache";
+		};
+
+		scache1: l3-cache1 {
+			compatible = "cache";
+		};
+
+		scache2: l3-cache2 {
+			compatible = "cache";
+		};
+
+		scache3: l3-cache3 {
+			compatible = "cache";
+		};
+	};
+};