feature: added VHDL, Verilog and SystemVerilog syntax

[AntonioBerna]

$ loc
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 Language             Files        Lines        Blank      Comment         Code
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 Plain Text               3         9000            0            0         9000
 TeX                      1         1587          345           10         1232
 VHDL                     2          304           33            0          271
 Verilog                  2          278           42            0          236
 C                        2          257           47            0          210
 Makefile                 1          156           31            0          125
 Markdown                 1           11            3            0            8
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 Total                   12        11593          501           10        11082
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Closes #161