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fix(PeriphDrivers): Fix UART clock source selection for MAX32650/60/65/66 #1482
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fix(PeriphDrivers): Fix UART clock source selection for MAX32650/60/65/66 #1482
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/clang-format-run |
| if (baudRate > PeripheralClock / 8) { | ||
| baudRate = 115200; | ||
| } |
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What happens if we do not fall back to 115200bps? How is the behavior in other parts?
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At reset, when baud registers set 0, GetFrequency will return peripheralClock/3. And maximum baudrate can be pclk/8. This part should only run at reset. if baudrate set once. It can getFrequecy properly. Eg. in zephyr uart_max32 driver tries to set clock first and then set baudrate, it fails. What do you suggest? @ttmut
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I see the issue.
Well at least set the baudrate to PeripheralClock / 8 so that it is somewhat consistent with the documentation.
The baud rate generator will automatically be reconfigured to the closest possible baud rate.
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| if (baudRate > PeripheralClock / 8) { | ||
| baudRate = 115200; | ||
| } |
There was a problem hiding this comment.
Choose a reason for hiding this comment
The reason will be displayed to describe this comment to others. Learn more.
I see the issue.
Well at least set the baudrate to PeripheralClock / 8 so that it is somewhat consistent with the documentation.
The baud rate generator will automatically be reconfigured to the closest possible baud rate.
Unlock ability to change uart clock to 7MHz internal clock MAX32650/MAX32665/MAX32666 Signed-off-by: Anil Ozrenk <anil.ozrenk@analog.com>
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Unlock 7MHz internal clock selection for MAX32650, MAX32652, MAX32665, MAX32666 Signed-off-by: Anil Ozrenk <anil.ozrenk@analog.com>
Max32660 can only use PCLK Signed-off-by: Anil Ozrenk <anil.ozrenk@analog.com>
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Description
Fixes UART clock source selection across legacy MAX32 microcontrollers and updates the Zephyr wrapper to properly support IBRO (7MHz) clock selection.
Changes
PeriphDrivers
uart_me10.c (MAX32650) & uart_me14.c (MAX32665/66): Fixed MXC_UART_SetClockSource() to:
uart_me11.c (MAX32660): Simplified MXC_UART_SetClockSource() to return
E_NO_ERRORsince MAX32660 only supports PCLK (no alternative clock source)uart_reva.c: Improved clock source switching logic:
Zephyr Wrapper
Affected Devices