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Merged
amonemi merged 21 commits into from
Nov 18, 2025
Merged

Ft/mesh 3d #7

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fe31a90
add 3d_noc to gui
Oct 17, 2025
2dcc16e
add mesh_3d top noc
Oct 20, 2025
4250847
support mesh_3d in verilator split mode
Oct 23, 2025
cf5048d
change XY routing name to DOR
Oct 23, 2025
8e56d4f
define regular_top_addr struct
Oct 24, 2025
cf4184c
update
Oct 25, 2025
34a21e8
add mesh_3d to perl topology config
Oct 26, 2025
278934d
update
Oct 26, 2025
b27dc0f
use casting for mesh addr
Oct 26, 2025
bbedaa4
mesh_3d single local port works
Oct 26, 2025
95a05ac
mesh_3d with multiple local ports works
Oct 30, 2025
8d7f1cf
replace regular endp addr gen with casting
Nov 1, 2025
3fb8fa0
ssa works in mesh-3d
Nov 2, 2025
d44fab0
--amend
Nov 2, 2025
8f2a55a
smart works in mesh_3d
Nov 2, 2025
e61622e
add more mesh_3d tests
Nov 7, 2025
d28ecaa
define fifo_stat_t struct
Nov 7, 2025
e1cecc3
add 3d_mesh to tinytop config
Nov 7, 2025
537b8b5
define IPORT_B and IPORT_V parameter for flit buffer
Nov 14, 2025
b18b741
use pronoc_pkg in congestion gen
Nov 14, 2025
a0a5ce2
remove more params passing
Nov 14, 2025
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2 changes: 1 addition & 1 deletion .github/workflows/main.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ jobs:
image: verilator/verilator:4.104
strategy:
matrix:
conf_name: [general, line-ring, multicast, vc_alloc, conv_route, tiny_topos]
conf_name: [general, line-ring, multicast, vc_alloc, conv_route, tiny_topos, mesh_3d]
env:
ROOT: ${{ github.workspace }}/mpsoc
PRONOC_WORK: ${{ github.workspace }}/mpsoc_work
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2 changes: 1 addition & 1 deletion mpsoc/Integration_test/FPGA-kc07/models/mesh_4x4_2cycle_xy_v1
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@@ -1,6 +1,6 @@
$model = bless( {
'compile' => "verilate_mesh.sh",
'noc_param'=> {
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/FPGA-kc07/src/deafult_noc_param
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Expand Up @@ -8,7 +8,7 @@ $model = bless( {
"B" => "4",
"LB" => "B",
"Fpay" => "32",
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"PCK_TYPE" => " \"MULTI_FLIT\"",
"MIN_PCK_SIZE" => "2",
"BYTE_EN" => "0",
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2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/fmesh_8x8_2cycle_xy
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
$model = bless( {
'noc_param'=> {
"TOPOLOGY" => "\"FMESH\"",
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
}
}, 'ProNOC' );
10 changes: 10 additions & 0 deletions mpsoc/Integration_test/Questa_lint/configurations/mesh_3d_4x3x2x2
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@@ -0,0 +1,10 @@
$model = bless( {
'noc_param'=> {
"TOPOLOGY" => '"MESH_3D"',
"T1" => "4",
"T2" => "3",
"T3" => "2",
"T4" => "2",
"ROUTE_NAME" => '"DOR"',
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_2cycle_xy
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Expand Up @@ -4,6 +4,6 @@ $model = bless( {
"T2" => "4",
"T3" => "3",
"TOPOLOGY" => "\"MESH\"",
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_nonspec
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Expand Up @@ -4,7 +4,7 @@ $model = bless( {
"T2" => "4",
"T3" => "3",
"TOPOLOGY" => "\"MESH\"",
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"COMBINATION_TYPE" => "\"COMB_NONSPEC\"",
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec1
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Expand Up @@ -4,7 +4,7 @@ $model = bless( {
"T2" => "4",
"T3" => "3",
"TOPOLOGY" => "\"MESH\"",
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"COMBINATION_TYPE" => "\"COMB_SPEC1\"",
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_4x4x3_vc_spec2
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@ $model = bless( {
"T2" => "4",
"T3" => "3",
"TOPOLOGY" => "\"MESH\"",
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"COMBINATION_TYPE" => "\"COMB_SPEC2\"",
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_2cycle_xy
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
$model = bless( {
'noc_param'=> {
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
$model = bless( {
'noc_param'=> {
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"ESCAP_VC_MASK" => "4'd1",
"V" => 4,
}
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2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_4c
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
$model = bless( {
'noc_param'=> {
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"V" => 4,
"C" => 4,
"CLASS_SETTING" => "16'b1000010000100001",
Expand Down
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero1
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
$model = bless( {
'noc_param'=> {
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"ESCAP_VC_MASK" => "4'd1",
"V" => 4,
"HETERO_VC"=> "1",
Expand Down
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_4vc_hetero2
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
$model = bless( {
'noc_param'=> {
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"V" => 4,
"ESCAP_VC_MASK" => "4'd1",
"HETERO_VC"=> "2",
Expand Down
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/mesh_8x8_b2
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
$model = bless( {
'noc_param'=> {
"ROUTE_NAME" => "\"XY\"",
"ROUTE_NAME" => "\"DOR\"",
"B"=> "2",
"LB"=> 2
}
Expand Down
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/ring_8x8_2cycle_xy
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Expand Up @@ -3,6 +3,6 @@ $model = bless( {
'noc_param'=> {
TOPOLOGY=>"\"RING\"",
"TOPOLOGY" => "\"TORUS\"",
"ROUTE_NAME" => "\"TRANC_XY\"",
"ROUTE_NAME" => "\"TRANC_DOR\"",
}
}, 'ProNOC' );
2 changes: 1 addition & 1 deletion mpsoc/Integration_test/Questa_lint/configurations/torus_8x8_2cycle_xy
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
$model = bless( {
'noc_param'=> {
"TOPOLOGY" => "\"TORUS\"",
"ROUTE_NAME" => "\"TRANC_XY\"",
"ROUTE_NAME" => "\"TRANC_DOR\"",
}
}, 'ProNOC' );
4 changes: 2 additions & 2 deletions mpsoc/Integration_test/VCS/Golden_ref/line4_smart3.log
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Expand Up @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"

Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./topology_localparam.v, 143
pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")"
pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
Expand Down
16 changes: 8 additions & 8 deletions mpsoc/Integration_test/VCS/Golden_ref/mesh_3x3_v2_ssa.log
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Original file line number Diff line number Diff line change
Expand Up @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"

Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./topology_localparam.v, 143
pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")"
pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
Expand Down Expand Up @@ -1347,26 +1347,26 @@ mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"

Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./mesh_torus.sv, 336
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")"
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./mesh_torus.sv, 336
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")"
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./mesh_torus.sv, 336
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")"
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
Expand Down
4 changes: 2 additions & 2 deletions mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_mcast_f.log
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Original file line number Diff line number Diff line change
Expand Up @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"

Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./topology_localparam.v, 143
pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")"
pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
Expand Down
16 changes: 8 additions & 8 deletions mpsoc/Integration_test/VCS/Golden_ref/mesh_4x4_2cycle_xy_v2.log
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Original file line number Diff line number Diff line change
Expand Up @@ -195,10 +195,10 @@ pronoc_pkg, "(PCK_TYPE == "SINGLE_FLIT")"

Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./topology_localparam.v, 143
pronoc_pkg, "(ROUTE_NAME == "TRANC_XY")"
pronoc_pkg, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
Expand Down Expand Up @@ -1827,26 +1827,26 @@ mesh_torus_look_ahead_routing, "(TOPOLOGY == "TORUS")"

Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./mesh_torus.sv, 336
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")"
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./mesh_torus.sv, 336
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")"
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
./../../rtl/src_noc/./mesh_torus.sv, 336
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_XY")"
mesh_torus_mask_non_assignable_destport_no_self_loop, "(ROUTE_NAME == "TRANC_DOR")"
A left 16-bit expression is compared to a right 64-bit expression.
Comparing 'ROUTE_NAME' of type string
with '"TRANC_XY"' of type string.
with '"TRANC_DOR"' of type string.


Lint-[ULCO] Unequal length in comparison operator
Expand Down
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