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afzalamu/README.md

Afzal Malik

Design Engineer | VLSI | Memory & Circuit Design Zia Semiconductor Pvt. Ltd.

About Me

I am a VLSI Design Engineer with hands-on experience in memory design, analog circuit design, and mixed-signal systems. My work spans CMOS circuit design, simulation, layout, and system-level integration, with academic and industry exposure to both analog and digital VLSI flows.

I have a strong foundation in CMOS fundamentals, circuit analysis, and verification, and I enjoy working close to silicon—building, analyzing, and validating circuits with clear performance targets.

Skills, Tools & Technologies

EDA & VLSI Tools

  • Cadence Virtuoso
  • LTspice
  • Electric VLSI and Glade
  • Analog Designer Toolbox (ADT)
  • Xilinx Vivado

Design Domains

  • SRAM & Custom Memory Design
  • CMOS Analog Circuit Design
  • Circuit Analysis & Simulation
  • FPGA & RTL Design

Languages & Scripting

  • Verilog HDL
  • Python
  • C
  • Bash / Linux Environment

Industry Experience

Design Engineer

Zia Semiconductor Pvt. Ltd. Jul 2025 – Present

  • Working on memory design and characterization flows for advanced semiconductor applications.
  • Involved in circuit-level analysis, validation, and performance evaluation under PVT variations.
  • Exposure to industry-standard design methodologies and review processes.

Internship Experience

Analog Circuit Design Intern

Jun 2023 – Jul 2023 Mentor: Dr. G.S. Javed (Analog Design Manager, Intel)

  • Designed and simulated key analog building blocks using gm/Id methodology in 180nm CMOS.

  • Circuits designed:

    • Common-source & source follower amplifiers
    • Single-stage and two-stage operational amplifiers
    • Basic analog filters

  • Focused on meeting gain, bandwidth, stability, and power targets.

🔗 Repository: https://github.com/afzalamu/Analog-Design-Internship

Publications

A 5 GHz Gain-Bandwidth Operational Amplifier in 180 nm CMOS Technology IEEE VLSI SATA 2024

Projects

Phase-Locked Loop (PLL) Design – 2.4 GHz (180 nm CMOS)

Aug 2024 – Jun 2025 🔗 https://github.com/afzalamu/Design-of-Phase-locked-loop-for-2.4-GHz-frequency-in-180nm-Technology

  • Complete design and simulation of a 2.4 GHz PLL for wireless applications.

  • Designed and integrated:

    • NMOS LC VCO
    • TSPC-based frequency divider
    • PFD using NAND logic
    • Charge pump & loop filter

  • Verified locking behavior, settling time, and stability.

  • Tools: LTspice

  • Technology: CMOS 180 nm

Neural Network Based Digit Recognition – FPGA Implementation

Jan 2024 – May 2024 🔗 https://www.linkedin.com/posts/malik-afzal_fpgaimplementation-neuralnetworkdesign-hardwaredesign-activity-7214560873271476224

  • Developed a handwritten digit recognition system using MNIST dataset.
  • Implemented neural network in Verilog HDL and deployed on FPGA.
  • Verified behavior through simulation and on-hardware testing.
  • Tools: Xilinx Vivado
  • Board: NEXYS A7
  • Languages: Verilog, Python

Two-Stage Operational Amplifier Design (180 nm CMOS)

Jun 2023 – Jul 2023 🔗 https://github.com/afzalamu/Design-of-two-stage-operational-amplifier-at-180nm-Technology

  • Designed using gm/Id methodology.

  • Target specifications:

    • Gain > 60 dB
    • GBW ≈ 1 GHz
    • Phase Margin > 50°

  • Performed schematic design, simulation, and layout.

  • Tools: LTspice, ADT, Electric VLSI

CMOS Inverter Design & Analysis (180 nm)

Nov 2022 🔗 https://github.com/afzalamu/cmos-inverter-design-and-analysis-using-tsmc180nm

  • Designed CMOS inverter using TSMC 180 nm models.

  • Analyzed:

    • VTC characteristics
    • Noise margins
    • Switching threshold

  • Completed layout and verification.

  • Tools: LTspice, Electric VLSI

Connect With Me

Pinned Loading

  1. Design-of-Phase-locked-loop-for-2.4-GHz-frequency-in-180nm-Technology Design-of-Phase-locked-loop-for-2.4-GHz-frequency-in-180nm-Technology Public

    Design of Phase locked loop for 2.4 GHz frequency in 180nm Technology

    AGS Script

  2. Analog-Design-Internship Analog-Design-Internship Public

    This 6 Week summer internship, organized by the Engineering Design and Implementation Club (Edic) in collaboration with the Department of Electronics Engineering at Aligarh Muslim University, offer…

    AGS Script 1 1

  3. FIR-Filter-using-MAC FIR-Filter-using-MAC Public

    Design and FPGA Implementation of FIR Filter using MAC (Multiplier-Accumulator) on FPGA (Artix 7)

    Verilog

  4. Design-of-two-stage-operational-amplifier-at-180nm-Technology Design-of-two-stage-operational-amplifier-at-180nm-Technology Public

    This project contains the design of two stage operational amplifier at 180nm Technology using gm over Id methodology for UGB 1GHz

    AGS Script 2

  5. Half-Adder-Schematic-to-GDS2 Half-Adder-Schematic-to-GDS2 Public

    Half Adder Schematic to GDS2 using GPDK90 in Cadence

  6. CMOS-Inverter-Design-and-GDSII-Generation-using-Cadence-Virtuoso-GPDK90- CMOS-Inverter-Design-and-GDSII-Generation-using-Cadence-Virtuoso-GPDK90- Public

    This repository contains the design and analysis of a CMOS inverter using Cadence Virtuoso with GPDK90 technology. The project includes schematic and layout design, pre-layout and post-layout simul…

    1