CTXP is a unified trace format for exporting processor trace data (control-flow, memory accesses, and timing) from single- and multi-core systems.
This repository aims to be a publication-quality reference for the CTXP format:
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A readable overview and quick reference
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Canonical, curated examples
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A small linter to keep examples consistent
The authoritative specification is included in spec/TN_CTXP_Format.pdf.
The text format (.ctxp.txt) is intended to be grep-able and diff-able.
HDR:format=accemic//ctxp-txt,ver=1
META:#0="CPU0"
#0:SYNC::0x80000000 @ 0
#0:BRANCH_NOTTAKEN:0x80000014:0x80000018 @ 3
#0:CALL:0x8000001c:0x8000004c @ 5
#0:RETURN:0x80000050:0x80000020 @ 17-
Control-flow:
SYNC,BRANCH_TAKEN,BRANCH_NOTTAKEN,CALL,RETURN,INTERRUPT,RFI -
Memory:
MEMREAD_0/1/2/4/8,MEMWRITE_0/1/2/4/8 -
Other:
OVERFLOW,CONTEXT,WALLCLOCK
The list below is a small excerpt. See examples/
for the full set of curated example traces and explanations.
The authoritative format specification is in spec/TN_CTXP_Format.pdf.
Accemic provides a CTXP exporter/decoder tool for converting native hardware trace formats to CTXP and consuming CTXP in analyzers.
Common native trace formats supported include:
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RISC-V Nexus traces
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Arm CoreSight ETMv4
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Arm CoreSight PFT
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Infineon TriCore MCDS (TC2/TC3/TC4)
Accemic also has a NexRv adaptation (based on https://github.com/riscv-non-isa/tg-nexus-trace/tree/main/refcode/c) that supports CTXP output; it will be published soon.
If you want to evaluate or integrate CTXP tooling, please contact us:
The included technical note (spec/TN_CTXP_Format.pdf) states it is licensed under
Creative Commons Attribution 4.0 International (CC BY 4.0). See the PDF for details.
The CTXP format was developed as part of the TRISTAN project, a European Union research initiative involving 46 partners to advance the RISC-V ecosystem. See https://tristan-project.eu/ for more information.