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7 changes: 5 additions & 2 deletions port/espressif/esp/src/hal/spi.zig
Original file line number Diff line number Diff line change
Expand Up @@ -160,7 +160,6 @@ pub const SPI = enum(u2) {
self.set_bit_order(config.bit_order);
}

// TODO: not sure if this is the best way to do this
pub inline fn connect_pins(_: SPI, pins: struct {
data: union(enum) {
single_one_wire: ?gpio.Pin,
Expand Down Expand Up @@ -188,7 +187,7 @@ pub const SPI = enum(u2) {
},
.single_two_wires => |maybe_pins| {
if (maybe_pins.mosi) |mosi| {
mosi.connect_input_to_peripheral(.{ .signal = .fspid });
mosi.connect_peripheral_to_output(.{ .signal = .fspid });
}
if (maybe_pins.miso) |miso| {
miso.connect_input_to_peripheral(.{ .signal = .fspiq });
Expand Down Expand Up @@ -223,6 +222,10 @@ pub const SPI = enum(u2) {
}
},
}

if (pins.clk) |clk_pin| {
clk_pin.connect_peripheral_to_output(.{ .signal = .spiclk });
}
}

pub fn writev_blocking(
Expand Down
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