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core.Mmio: Respect field access type #895

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19975bb
speed up cache regen by not compiling sqlite twice
piotrfila Jan 31, 2026
0d097f1
reduce use of Mmio
piotrfila Feb 1, 2026
2058614
Mmio -> OldMmio in non-generated code
piotrfila Feb 1, 2026
d644a36
Add access field to Mmio
piotrfila Feb 1, 2026
56a1862
remove unused Mmio.toggle
piotrfila Feb 1, 2026
1cb0480
Mmio: do more checks on underlying_type
piotrfila Feb 1, 2026
d1de386
remove Mmio.write_raw in favor of just accessing the .raw field
piotrfila Feb 1, 2026
c7480a7
rename addr in Mmio to self
piotrfila Feb 1, 2026
774ee65
initial implementation of register access types
piotrfila Feb 2, 2026
e34ae3a
mark padding and reserved fields as read only
piotrfila Feb 2, 2026
d16c3d3
output correct access type from regz
piotrfila Feb 2, 2026
c4a988b
redo mmio operations
piotrfila Feb 2, 2026
269cf1e
fix some CI issues
piotrfila Feb 2, 2026
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8 changes: 4 additions & 4 deletions core/src/cpus/cortex_m.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -1155,7 +1155,7 @@ pub const types = struct {
/// System Timer (SysTick).
pub const SysTick = extern struct {
/// Control and Status Register.
CTRL: mmio.Mmio(packed struct(u32) {
CTRL: mmio.OldMmio(packed struct(u32) {
/// Enables the counter:
/// 0 = counter disabled.
/// 1 = counter enabled.
Expand All @@ -1176,20 +1176,20 @@ pub const types = struct {
reserved1: u15 = 0,
}),
/// Reload Value Register.
LOAD: mmio.Mmio(packed struct(u32) {
LOAD: mmio.OldMmio(packed struct(u32) {
/// Value to load into the VAL register when the counter is enabled and when it reaches 0.
RELOAD: u24,
reserved0: u8 = 0,
}),
/// Current Value Register.
VAL: mmio.Mmio(packed struct(u32) {
VAL: mmio.OldMmio(packed struct(u32) {
/// Reads return the current value of the SysTick counter.
/// A write of any value clears the field to 0, and also clears the CTRL.COUNTFLAG bit to 0.
CURRENT: u24,
reserved0: u8 = 0,
}),
/// Calibration Register.
CALIB: mmio.Mmio(packed struct(u32) {
CALIB: mmio.OldMmio(packed struct(u32) {
/// Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value
/// reads as zero, the calibration value is not known.
TENMS: u24,
Expand Down
8 changes: 4 additions & 4 deletions core/src/cpus/cortex_m/m0.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ pub const SystemControlBlock = extern struct {
/// CPUID Base Register.
CPUID: u32,
/// Interrupt Control and State Register.
ICSR: mmio.Mmio(packed struct(u32) {
ICSR: mmio.OldMmio(packed struct(u32) {
/// Contains the active exception number:
/// 0 = Thread mode
/// Nonzero = The exception number[a] of the currently active exception.
Expand Down Expand Up @@ -79,7 +79,7 @@ pub const SystemControlBlock = extern struct {
}),
reserved0: u32 = 0,
/// Application Interrupt and Reset Control Register.
AIRCR: mmio.Mmio(packed struct {
AIRCR: mmio.OldMmio(packed struct {
reserved0: u1 = 0,
/// Reserved for debug use. This bit reads as 0. When writing to the register you must
/// write 0 to this bit, otherwise behavior is Unpredictable.
Expand All @@ -101,7 +101,7 @@ pub const SystemControlBlock = extern struct {
VECTKEY: u16,
}),
/// System Control Register.
SCR: mmio.Mmio(packed struct(u32) {
SCR: mmio.OldMmio(packed struct(u32) {
reserved0: u1 = 0,
/// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
/// 0 = do not sleep when returning to Thread mode.
Expand Down Expand Up @@ -130,7 +130,7 @@ pub const SystemControlBlock = extern struct {
reserved2: u27 = 0,
}),
/// Configuration Control Register.
CCR: mmio.Mmio(packed struct(u32) {
CCR: mmio.OldMmio(packed struct(u32) {
reserved0: u3 = 0,
/// Always reads as one, indicates that all unaligned accesses generate a HardFault.
UNALIGN_TRP: u1,
Expand Down
18 changes: 9 additions & 9 deletions core/src/cpus/cortex_m/m0plus.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ pub const SystemControlBlock = extern struct {
/// CPUID Base Register.
CPUID: u32,
/// Interrupt Control and State Register.
ICSR: mmio.Mmio(packed struct(u32) {
ICSR: mmio.OldMmio(packed struct(u32) {
/// Contains the active exception number:
/// 0 = Thread mode
/// Nonzero = The exception number[a] of the currently active exception.
Expand Down Expand Up @@ -80,7 +80,7 @@ pub const SystemControlBlock = extern struct {
/// Vector Table Offset Register.
VTOR: u32,
/// Application Interrupt and Reset Control Register.
AIRCR: mmio.Mmio(packed struct {
AIRCR: mmio.OldMmio(packed struct {
reserved0: u1 = 0,
/// Reserved for debug use. This bit reads as 0. When writing to the register you must
/// write 0 to this bit, otherwise behavior is Unpredictable.
Expand All @@ -102,7 +102,7 @@ pub const SystemControlBlock = extern struct {
VECTKEY: u16,
}),
/// System Control Register.
SCR: mmio.Mmio(packed struct(u32) {
SCR: mmio.OldMmio(packed struct(u32) {
reserved0: u1 = 0,
/// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
/// 0 = do not sleep when returning to Thread mode.
Expand Down Expand Up @@ -131,7 +131,7 @@ pub const SystemControlBlock = extern struct {
reserved2: u27 = 0,
}),
/// Configuration Control Register.
CCR: mmio.Mmio(packed struct(u32) {
CCR: mmio.OldMmio(packed struct(u32) {
reserved0: u3 = 0,
/// Always reads as one, indicates that all unaligned accesses generate a HardFault.
UNALIGN_TRP: u1,
Expand Down Expand Up @@ -196,7 +196,7 @@ pub const NestedVectorInterruptController = extern struct {

pub const MemoryProtectionUnit = extern struct {
/// MPU Type Register
TYPE: mmio.Mmio(packed struct(u32) {
TYPE: mmio.OldMmio(packed struct(u32) {
/// Indicates support for unified or separate instructions and data address regions.
SEPARATE: u1,
reserved0: u7 = 0,
Expand All @@ -207,7 +207,7 @@ pub const MemoryProtectionUnit = extern struct {
reserved1: u8 = 0,
}),
/// MPU Control Register
CTRL: mmio.Mmio(packed struct(u32) {
CTRL: mmio.OldMmio(packed struct(u32) {
/// Enables the MPU
ENABLE: u1,
/// Enables of operation of MPU during HardFault and MNIHandlers.
Expand All @@ -217,13 +217,13 @@ pub const MemoryProtectionUnit = extern struct {
reserved0: u29 = 0,
}),
/// MPU Region Number Register
RNR: mmio.Mmio(packed struct(u32) {
RNR: mmio.OldMmio(packed struct(u32) {
/// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
REGION: u8,
reserved0: u24 = 0,
}),
/// MPU Region Base Address Register
RBAR: mmio.Mmio(packed struct(u32) {
RBAR: mmio.OldMmio(packed struct(u32) {
/// MPU region field.
REGION: u4,
/// MPU region number valid bit.
Expand All @@ -232,7 +232,7 @@ pub const MemoryProtectionUnit = extern struct {
ADDR: u27,
}),
/// MPU Attribute and Size Register
RASR: mmio.Mmio(packed struct(u32) {
RASR: mmio.OldMmio(packed struct(u32) {
/// Region enable bit.
ENABLE: u1,
/// Specifies the size of the MPU region. The minimum permitted value is 7 (b00111).
Expand Down
24 changes: 12 additions & 12 deletions core/src/cpus/cortex_m/m3.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ pub const SystemControlBlock = extern struct {
/// CPUID Base Register.
CPUID: u32,
/// Interrupt Control and State Register.
ICSR: mmio.Mmio(packed struct(u32) {
ICSR: mmio.OldMmio(packed struct(u32) {
VECTACTIVE: u9,
reserved0: u2 = 0,
RETTOBASE: u1,
Expand All @@ -28,7 +28,7 @@ pub const SystemControlBlock = extern struct {
/// Vector Table Offset Register.
VTOR: u32,
/// Application Interrupt and Reset Control Register.
AIRCR: mmio.Mmio(packed struct {
AIRCR: mmio.OldMmio(packed struct {
VECTRESET: u1,
VECTCLRACTIVE: u1,
SYSRESETREQ: u1,
Expand All @@ -39,7 +39,7 @@ pub const SystemControlBlock = extern struct {
VECTKEY: u16,
}),
/// System Control Register.
SCR: mmio.Mmio(packed struct {
SCR: mmio.OldMmio(packed struct {
reserved0: u1 = 0,
SLEEPONEXIT: u1,
SLEEPDEEP: u1,
Expand All @@ -48,7 +48,7 @@ pub const SystemControlBlock = extern struct {
reserved2: u27 = 0,
}),
/// Configuration Control Register.
CCR: mmio.Mmio(packed struct(u32) {
CCR: mmio.OldMmio(packed struct(u32) {
NONBASETHRDENA: u1,
USERSETMPEND: u1,
reserved0: u1 = 0,
Expand All @@ -62,9 +62,9 @@ pub const SystemControlBlock = extern struct {
/// System Handlers Priority Registers.
SHPR: [3]u32,
/// System Handler Control and State Register.
SHCSR: mmio.Mmio(shared.scb.SHCSR),
SHCSR: mmio.OldMmio(shared.scb.SHCSR),
/// Configurable Fault Status Register.
CFSR: mmio.Mmio(packed struct(u32) {
CFSR: mmio.OldMmio(packed struct(u32) {
/// MemManage Fault Register.
MMFSR: shared.scb.MMFSR,
/// BusFault Status Register.
Expand All @@ -73,7 +73,7 @@ pub const SystemControlBlock = extern struct {
UFSR: shared.scb.UFSR,
}),
/// HardFault Status Register.
HFSR: mmio.Mmio(shared.scb.HFSR),
HFSR: mmio.OldMmio(shared.scb.HFSR),
reserved1: u32 = 0,
/// MemManage Fault Address Register.
MMFAR: u32,
Expand Down Expand Up @@ -108,7 +108,7 @@ pub const NestedVectorInterruptController = extern struct {

pub const MemoryProtectionUnit = extern struct {
/// MPU Type Register
TYPE: mmio.Mmio(packed struct(u32) {
TYPE: mmio.OldMmio(packed struct(u32) {
/// Indicates support for unified or separate instructions and data address regions.
SEPARATE: u1,
reserved0: u7 = 0,
Expand All @@ -119,7 +119,7 @@ pub const MemoryProtectionUnit = extern struct {
reserved1: u8 = 0,
}),
/// MPU Control Register
CTRL: mmio.Mmio(packed struct(u32) {
CTRL: mmio.OldMmio(packed struct(u32) {
/// Enables the MPU
ENABLE: u1,
/// Enables of operation of MPU during HardFault and MNIHandlers.
Expand All @@ -129,7 +129,7 @@ pub const MemoryProtectionUnit = extern struct {
reserved0: u29 = 0,
}),
/// MPU Region Number Register
RNR: mmio.Mmio(packed struct(u32) {
RNR: mmio.OldMmio(packed struct(u32) {
/// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
REGION: u8,
reserved0: u24 = 0,
Expand All @@ -151,7 +151,7 @@ pub const MemoryProtectionUnit = extern struct {
/// MPU Alias 3 Region Attribute and Size Register
RASR_A3: RASR_Register,

pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
/// MPU region field.
REGION: u4,
/// MPU region number valid bit.
Expand All @@ -160,7 +160,7 @@ pub const MemoryProtectionUnit = extern struct {
ADDR: u27,
});

pub const RASR_Register = mmio.Mmio(packed struct(u32) {
pub const RASR_Register = mmio.OldMmio(packed struct(u32) {
/// Region enable bit.
ENABLE: u1,
/// Specifies the size of the MPU protection region.
Expand Down
28 changes: 14 additions & 14 deletions core/src/cpus/cortex_m/m33.zig
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ pub const SystemControlBlock = extern struct {
/// CPUID Base Register.
CPUID: u32,
/// Interrupt Control and State Register.
ICSR: mmio.Mmio(packed struct(u32) {
ICSR: mmio.OldMmio(packed struct(u32) {
/// Contains the active exception number:
/// 0 = Thread mode
/// Nonzero = The exception number[a] of the currently active exception.
Expand Down Expand Up @@ -109,7 +109,7 @@ pub const SystemControlBlock = extern struct {
/// Vector Table Offset Register.
VTOR: u32,
/// Application Interrupt and Reset Control Register.
AIRCR: mmio.Mmio(packed struct {
AIRCR: mmio.OldMmio(packed struct {
reserved0: u1 = 0,
/// Reserved for debug use. This bit reads as 0. When writing to the register you must
/// write 0 to this bit, otherwise behavior is Unpredictable.
Expand Down Expand Up @@ -160,7 +160,7 @@ pub const SystemControlBlock = extern struct {
VECTKEY: u16,
}),
/// System Control Register.
SCR: mmio.Mmio(packed struct(u32) {
SCR: mmio.OldMmio(packed struct(u32) {
reserved0: u1 = 0,
/// Indicates sleep-on-exit when returning from Handler mode to Thread mode:
/// 0 = do not sleep when returning to Thread mode.
Expand Down Expand Up @@ -192,7 +192,7 @@ pub const SystemControlBlock = extern struct {
reserved1: u27 = 0,
}),
/// Configuration and Control Register.
CCR: mmio.Mmio(packed struct(u32) {
CCR: mmio.OldMmio(packed struct(u32) {
reserved0: u1 = 0,
/// User set pending determines if unpriviledged access to the STIR generates a fault.
USERSETMPEND: u1,
Expand All @@ -219,9 +219,9 @@ pub const SystemControlBlock = extern struct {
/// System Handler Priority Registers.
SHPR: [12]u8,
/// System Handler Control and State Register.
SHCSR: mmio.Mmio(shared.scb.SHCSR),
SHCSR: mmio.OldMmio(shared.scb.SHCSR),
/// Configurable Fault Status Register.
CFSR: mmio.Mmio(packed struct(u32) {
CFSR: mmio.OldMmio(packed struct(u32) {
/// MemManage Fault Register.
MMFSR: shared.scb.MMFSR,
/// BusFault Status Register.
Expand All @@ -230,7 +230,7 @@ pub const SystemControlBlock = extern struct {
UFSR: shared.scb.UFSR,
}),
/// HardFault Status Register.
HFSR: mmio.Mmio(shared.scb.HFSR),
HFSR: mmio.OldMmio(shared.scb.HFSR),
reserved0: u32 = 0,
/// MemManage Fault Address Register.
MMFAR: u32,
Expand All @@ -240,7 +240,7 @@ pub const SystemControlBlock = extern struct {
_AFSR: u32,
reserved1: [18]u32,
/// Coprocessor Access Control Register.
CPACR: mmio.Mmio(packed struct(u32) {
CPACR: mmio.OldMmio(packed struct(u32) {
CP0: Privilege,
CP1: Privilege,
CP2: Privilege,
Expand Down Expand Up @@ -269,7 +269,7 @@ pub const SystemControlBlock = extern struct {
};

pub const FloatingPointUnit = extern struct {
FPCCR: mmio.Mmio(packed struct(u32) {
FPCCR: mmio.OldMmio(packed struct(u32) {
LSPACT: u1,
USER: u1,
S: u1,
Expand Down Expand Up @@ -382,7 +382,7 @@ pub const SecurityAttributionUnit = extern struct {

pub const MemoryProtectionUnit = extern struct {
/// MPU Type Register.
TYPE: mmio.Mmio(packed struct(u32) {
TYPE: mmio.OldMmio(packed struct(u32) {
/// Indicates support for unified or separate instructions and data address regions.
SEPARATE: u1,
reserved0: u7 = 0,
Expand All @@ -391,7 +391,7 @@ pub const MemoryProtectionUnit = extern struct {
reserved1: u16 = 0,
}),
/// MPU Control Register.
CTRL: mmio.Mmio(packed struct(u32) {
CTRL: mmio.OldMmio(packed struct(u32) {
/// Enables the MPU
ENABLE: u1,
/// Enables of operation of MPU during HardFault and MNIHandlers.
Expand All @@ -401,7 +401,7 @@ pub const MemoryProtectionUnit = extern struct {
reserved0: u29 = 0,
}),
/// MPU Region Number Register.
RNR: mmio.Mmio(packed struct(u32) {
RNR: mmio.OldMmio(packed struct(u32) {
/// Indicates the memory region accessed by MPU RBAR and PMU RLAR.
REGION: u8,
reserved0: u24 = 0,
Expand Down Expand Up @@ -429,7 +429,7 @@ pub const MemoryProtectionUnit = extern struct {
MPU_MAIR1: u32,

/// MPU Region Address Register format.
pub const RBAR_Register = mmio.Mmio(packed struct(u32) {
pub const RBAR_Register = mmio.OldMmio(packed struct(u32) {
/// Execute Never defines if code can be executed from this region.
XN: u1,
/// Access permissions.
Expand All @@ -442,7 +442,7 @@ pub const MemoryProtectionUnit = extern struct {
});

/// MPU Region Limit Address Register format.
pub const RLAR_Register = mmio.Mmio(packed struct(u32) {
pub const RLAR_Register = mmio.OldMmio(packed struct(u32) {
/// Enable the region.
EN: u1,
/// Attribue Index associates a set of attributes in the MPU MAIR0 and MPU MAIR1 fields.
Expand Down
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