changed to verilator + enabled spi test

.github/workflows/test.yaml

@@ -9,9 +9,18 @@ jobs:
         with:
           submodules: recursive
 
-      - name: Install iverilog
+      - name: Install Verilator
         shell: bash
-        run: sudo apt-get update && sudo apt-get install -y iverilog
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y git help2man perl python3 make autoconf g++ flex bison ccache libgoogle-perftools-dev numactl perl-doc libfl2 libfl-dev zlib1g zlib1g-dev
+          git clone https://github.com/verilator/verilator.git --depth 1 --branch v5.036
+          cd verilator
+          autoconf
+          ./configure
+          make -j$(nproc)
+          sudo make install
+          verilator --version
 
       # Set Python up and install cocotb
       - name: Setup python
@@ -29,8 +38,8 @@ jobs:
           make cleanall
           make test_command_port
           make test_transaction_fsm
+          make test_spi_controller
           # TODO: Add these once they pass:
-          # make test_spi_controller
           # make test_mem_top (requires W25Q128JVxIM.v flash model)
           # make test_tt_toplevel
           # Check for failures in results.xml

test/Makefile

@@ -18,10 +18,14 @@
 # ============================================================================
 
 # Defaults
-SIM ?= icarus
+SIM ?= verilator
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
 
+# Verilator trace options
+EXTRA_ARGS += --trace
+EXTRA_ARGS += --trace-structs
+
 PROJECT_SOURCES = mem_command_port.v \
                   mem_spi_controller.v \
                   mem_txn_fsm.v \
@@ -67,7 +71,7 @@ test_transaction_fsm:
 		MODULE=test_mem_transaction_fsm \
 		TOPLEVEL=mem_txn_fsm \
 		VERILOG_SOURCES="$(SRC_DIR)/mem_txn_fsm.v" \
-		COMPILE_ARGS="$(COMPILE_ARGS) -DSIMULATION"
+		EXTRA_ARGS="--trace --trace-structs -DSIMULATION"
 
 test_mem_top:
 	$(MAKE) clean

test/requirements.txt

@@ -1,2 +1,2 @@
 pytest==8.3.4
-cocotb==1.9.2
+cocotb==2.0.1

test/test_mem_command_port.py

@@ -46,9 +46,9 @@
     Timer,
     ClockCycles,
     with_timeout,
+    SimTimeoutError,
 )
-from cocotb.result import SimTimeoutError
-from cocotb.utils import get_sim_time
+from cocotb.simtime import get_sim_time
 
 RD_KEY_AES_BYTES = 32
 RD_TEXT_AES_BYTES = 16