Actions passing

docs/info.md

@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Explain how your project works
+insert 1
 
 ## How to test
 
-Explain how to use your project
+insert 2
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+insert 3

info.yaml

@@ -3,24 +3,24 @@ project:
   title:        "Crypto Accelerator Memory Interface"      # Project title
   author:       "UWASIC"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "Interfacing external memory with the rest of the cryotographic accelerator"      # One line description of what your project does
+  description:  "Interfacing external memory with the rest of the cryptographic accelerator"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_mem_toplevel.v"
+  top_module:  "tt_um_mem_toplevel"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
     - mem_command_port.v
     - mem_spi_controller.v
-    - mem_status_poller.v
-    - mem_transaction_fsm.v
+    - mem_txn_fsm.v
+    - mem_top.v
     - tt_um_mem_toplevel.v
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.

test/Makefile

@@ -3,16 +3,17 @@
 
 # ============================================================================
 # Usage:
-#   make test_command_port       - Run command port tests
-#   make test_spi_controller     - Run SPI controller tests
-#   make test_transaction_fsm    - Run transaction FSM tests
-#   make test_mem_top            - Run mem_top tests (needs flash model)
-#   make test_tt_toplevel        - Run TinyTapeout toplevel tests
-#   make all_tests               - Run all tests
-#   make cleanall                - Clean build artifacts
+#   make                         - Run default test (RTL: tt_toplevel)
+#   make test_command_port       - Run command port tests (RTL only)
+#   make test_spi_controller     - Run SPI controller tests (RTL only)
+#   make test_transaction_fsm    - Run transaction FSM tests (RTL only)
+#   make test_mem_top            - Run mem_top tests (RTL only, needs flash model)
+#   make test_tt_toplevel        - Run TinyTapeout toplevel tests (RTL only)
+#   make all_tests               - Run all RTL tests
+#   make clean                   - Clean build artifacts
 #
-# Gate-level simulation:
-#   make test_command_port GATES=yes
+# Gate-level simulation (tests synthesized top-level only):
+#   make GATES=yes
 #   Requires: PDK_ROOT env var, gate_level_netlist.v in test/
 # ============================================================================
 
@@ -21,107 +22,99 @@ SIM ?= icarus
 TOPLEVEL_LANG ?= verilog
 SRC_DIR = $(PWD)/../src
 
-# Default source files
-SRC_FILES ?= mem_command_port.v mem_spi_controller.v mem_txn_fsm.v mem_top.v mem_vendor_test.v W25Q128JVxIM.v
+PROJECT_SOURCES = mem_command_port.v \
+                  mem_spi_controller.v \
+                  mem_txn_fsm.v \
+                  mem_top.v \
+                  tt_um_mem_toplevel.v
 
-# Testbench file (optional, for tt_toplevel)
-TB_FILE ?=
-
-# Include path
+# Allow sharing configuration between design and testbench via `include`:
 COMPILE_ARGS += -I$(SRC_DIR)
 
-# ============================================================================
-# Gate Level vs RTL Simulation
-# ============================================================================
 ifneq ($(GATES),yes)
+
+# ============================================================================
 # RTL simulation
+# ============================================================================
 SIM_BUILD = sim_build/rtl
-VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(SRC_FILES))
-ifneq ($(TB_FILE),)
-VERILOG_SOURCES += $(PWD)/$(TB_FILE)
-endif
+VERILOG_SOURCES += $(addprefix $(SRC_DIR)/,$(PROJECT_SOURCES))
+VERILOG_SOURCES += $(PWD)/tb_tt_um_mem_toplevel.v
 COMPILE_ARGS += -DSIMULATION
-else
-
-
-# Gate level simulation
-SIM_BUILD = sim_build/gl
-COMPILE_ARGS += -DGL_TEST
-COMPILE_ARGS += -DFUNCTIONAL
-COMPILE_ARGS += -DUSE_POWER_PINS
-COMPILE_ARGS += -DSIM
-COMPILE_ARGS += -DUNIT_DELAY=\#1
-VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
-VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
-VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
-ifneq ($(TB_FILE),)
-VERILOG_SOURCES += $(PWD)/$(TB_FILE)
-endif
-endif
-
-# Default toplevel and module (for direct 'make' invocation)
-TOPLEVEL ?= mem_vendor_test
-MODULE ?= test_mem_top
 
-# ============================================================================
-# Test Targets (only at top level, not in recursive calls)
-# ============================================================================
-.PHONY: test_command_port test_spi_controller test_transaction_fsm test_mem_top test_tt_toplevel all_tests cleanall
+# Default for RTL
+TOPLEVEL ?= tb
+MODULE ?= test_tt_um_mem_toplevel
 
-ifeq ($(MAKELEVEL),0)
+.PHONY: test_command_port test_spi_controller test_transaction_fsm test_mem_top test_tt_toplevel all_tests clean cleanall
 
 test_command_port:
-	rm -rf sim_build
-	$(MAKE) -f $(firstword $(MAKEFILE_LIST)) \
-		TOPLEVEL=mem_command_port \
+	$(MAKE) clean
+	$(MAKE) sim \
 		MODULE=test_mem_command_port \
-		SRC_FILES="mem_command_port.v"
+		TOPLEVEL=mem_command_port \
+		VERILOG_SOURCES="$(SRC_DIR)/mem_command_port.v"
 
 test_spi_controller:
-	rm -rf sim_build
-	$(MAKE) -f $(firstword $(MAKEFILE_LIST)) \
-		TOPLEVEL=mem_spi_controller \
+	$(MAKE) clean
+	$(MAKE) sim \
 		MODULE=test_mem_spi_controller \
-		SRC_FILES="mem_spi_controller.v"
+		TOPLEVEL=mem_spi_controller \
+		VERILOG_SOURCES="$(SRC_DIR)/mem_spi_controller.v"
 
 test_transaction_fsm:
-	rm -rf sim_build
-	$(MAKE) -f $(firstword $(MAKEFILE_LIST)) \
-		TOPLEVEL=mem_txn_fsm \
+	$(MAKE) clean
+	$(MAKE) sim \
 		MODULE=test_mem_transaction_fsm \
-		SRC_FILES="mem_txn_fsm.v"
+		TOPLEVEL=mem_txn_fsm \
+		VERILOG_SOURCES="$(SRC_DIR)/mem_txn_fsm.v" \
+		COMPILE_ARGS="$(COMPILE_ARGS) -DSIMULATION"
 
 test_mem_top:
-	rm -rf sim_build
-	$(MAKE) -f $(firstword $(MAKEFILE_LIST)) \
-		TOPLEVEL=mem_vendor_test \
+	$(MAKE) clean
+	$(MAKE) sim \
 		MODULE=test_mem_top \
-		SRC_FILES="mem_command_port.v mem_spi_controller.v mem_txn_fsm.v mem_top.v mem_vendor_test.v W25Q128JVxIM.v"
+		TOPLEVEL=mem_vendor_test \
+		VERILOG_SOURCES="$(SRC_DIR)/mem_command_port.v $(SRC_DIR)/mem_spi_controller.v $(SRC_DIR)/mem_txn_fsm.v $(SRC_DIR)/mem_top.v $(SRC_DIR)/mem_vendor_test.v $(SRC_DIR)/W25Q128JVxIM.v"
 
 test_tt_toplevel:
-	rm -rf sim_build
-	$(MAKE) -f $(firstword $(MAKEFILE_LIST)) \
-		TOPLEVEL=tb \
+	$(MAKE) clean
+	$(MAKE) sim \
 		MODULE=test_tt_um_mem_toplevel \
-		SRC_FILES="mem_command_port.v mem_spi_controller.v mem_txn_fsm.v mem_top.v tt_um_mem_toplevel.v" \
-		TB_FILE="tb_tt_um_mem_toplevel.v"
-
-all_tests:
-	@echo "Running test_command_port..."
-	$(MAKE) test_command_port
-	@echo "Running test_spi_controller..."
-	$(MAKE) test_spi_controller
-	@echo "Running test_transaction_fsm..."
-	$(MAKE) test_transaction_fsm
-	@echo "Running test_mem_top..."
-	$(MAKE) test_mem_top
+		TOPLEVEL=tb \
+		VERILOG_SOURCES="$(SRC_DIR)/mem_command_port.v $(SRC_DIR)/mem_spi_controller.v $(SRC_DIR)/mem_txn_fsm.v $(SRC_DIR)/mem_top.v $(SRC_DIR)/tt_um_mem_toplevel.v $(PWD)/tb_tt_um_mem_toplevel.v"
+
+all_tests: test_command_port test_spi_controller test_transaction_fsm test_mem_top test_tt_toplevel
 	@echo "All tests completed!"
 
-cleanall:
-	rm -rf sim_build __pycache__
-	rm -f results.xml *.vcd
+else
+
+# ============================================================================
+# Gate level simulation (can only test synthesized top-level)
+# ============================================================================
+SIM_BUILD = sim_build/gl
+COMPILE_ARGS += -DGL_TEST
+COMPILE_ARGS += -DFUNCTIONAL
+COMPILE_ARGS += -DUSE_POWER_PINS
+COMPILE_ARGS += -DSIM
+COMPILE_ARGS += -DUNIT_DELAY=\#1
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v
+VERILOG_SOURCES += $(PDK_ROOT)/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
+VERILOG_SOURCES += $(PWD)/gate_level_netlist.v
+VERILOG_SOURCES += $(PWD)/tb_tt_um_mem_toplevel.v
+
+# For GL, can only test the synthesized top-level module
+TOPLEVEL ?= tb
+MODULE ?= test_tt_um_mem_toplevel
+
+.PHONY: clean cleanall
 
 endif
 
-# Include cocotb's make rules
+# Phony target for cleaning up
+clean::
+	rm -rf sim_build results.xml *.vcd __pycache__
+
+cleanall: clean
+
+# include cocotb's make rules to take care of the simulator setup
 include $(shell cocotb-config --makefiles)/Makefile.sim