This repository contains the SystemVerilog code and simulation results for a systolic array-based matrix-vector multiplication for signed 8 bit integers. The architecture is designed to perform the multiplication of a 16x16 matrix with a 16x1 vector in 16 clock cycles.
currently this architecture is implemented in Behavioural level for general purpose, which utilize LUT in FPGA.
You can replace the processing element with DSP blocks of FPGA depending on the requirement
The simulation results demonstrate the performance and correctness of the systolic array-based multiplication. which is done using - ModelSim for simulation.
