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Srikar109755/README.md

💫 About Me

I am a Final-Year Electronics and Communication Engineering student at IIITDM Kancheepuram, passionate about VLSI design and digital systems.
My core expertise lies in RTL design using Verilog/SystemVerilog, digital electronics, and hardware-software integration.

🔹 What I Do

  • Design & Implementation – VLSI and digital system design, RTL coding (Verilog/SystemVerilog), FPGA-based designs.
  • Learning & Exploration – ASIC frontend design, SoC architecture, Design for Testability (DFT), and low-power techniques.
  • Collaboration – Open-source hardware design, RTL design challenges, and digital logic-based projects.

📌 Current Focus

  • ASIC design flow and frontend implementation
  • Advanced RTL architecture and low-power methodologies
  • System-level hardware design and optimization

🛠 Technical Skills

Languages & HDL: Verilog, SystemVerilog, C, Python, MATLAB
EDA & Tools: ModelSim, Xilinx Vivado, Quartus, Cadence (basics)
Other Skills: Digital electronics, SoC design principles, FPGA prototyping
Software Tools: LaTeX, Arduino, Canva
Data Tools: NumPy, Pandas, Matplotlib

🌐 Connect With Me

LinkedIn
Email
GitHub

📊 GitHub Stats


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  1. RISC-V-Pipeline-Processor RISC-V-Pipeline-Processor Public

    Verilog implementation of an RISK-V out-of-order CPU core.

    Verilog 2 1

  2. 32-bit-Single_Cycle-MIPS-processor 32-bit-Single_Cycle-MIPS-processor Public

    32-bit single-cycle MIPS processor in Verilog with simulation support.

    Verilog

  3. UART-Transmitter-Receiver UART-Transmitter-Receiver Public

    UART system with Baud Generator, TX, and RX blocks. Converts parallel data to serial, transmits, and recovers it with parity checking.

    SystemVerilog

  4. FIFO_Model FIFO_Model Public

    Synthesizable FIFO model in Verilog with parameterizable width & depth, status flags, and full verification testbench.

    Verilog

  5. Auto_Temperature_Controller Auto_Temperature_Controller Public

    A 3-state FSM that turns on heater or cooler based on how far current temperature is from desired value with a tolerance margin.

    SystemVerilog

  6. Traffic-Light-Controller Traffic-Light-Controller Public

    A SystemVerilog-based finite state machine (FSM) to control traffic lights at a two-way intersection using timers and vehicle sensors.

    SystemVerilog