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f77e898
instruction: split arm, riscv opcodes and add registers
Samir-Rashid Feb 9, 2025
98fe35e
translate: add minimal riscv translation map
Samir-Rashid Feb 9, 2025
89f7276
meta: rename `test/` -> `tests/`
Samir-Rashid Feb 9, 2025
3279689
test imports
atar13 Feb 9, 2025
4034b1d
instruction: specify arguments to RISC-V ops
Samir-Rashid Feb 9, 2025
2c4fa41
wip translations
atar13 Feb 9, 2025
0cd2663
map_val empty
atar13 Feb 9, 2025
7db7eec
more translations + builds now
atar13 Feb 9, 2025
1ecd2c9
test: run translation from RISCV to ARM enums
Samir-Rashid Feb 9, 2025
4f573fe
map_register use helpers
atar13 Feb 19, 2025
f5ac84e
update calls to map_register with widths
atar13 Feb 19, 2025
5fd4018
fix move of width values
atar13 Feb 19, 2025
550b8d8
map width
trdavidt Feb 19, 2025
7a5d205
translate: `map_register_name` with semantic meanings
Samir-Rashid Feb 19, 2025
7f93a02
Merge branch 'register-enum-translation' of github.com:Samir-Rashid/b…
trdavidt Feb 19, 2025
2273195
map width
trdavidt Feb 19, 2025
aaeb3c8
starting instruction encoding
atar13 Feb 19, 2025
44b6a69
have assembly output now
atar13 Feb 21, 2025
6ced896
patched and assembled aarch64 add
atar13 Mar 3, 2025
f631c32
fix patched add example
trdavidt Mar 4, 2025
6fa93ff
fixed width/segfault issues
atar13 Mar 5, 2025
2c692d6
call syscall
trdavidt Mar 11, 2025
b02600a
merge and working print
atar13 Mar 12, 2025
6025db8
print and echo tests
atar13 Mar 12, 2025
b6e4099
basic control flow
trdavidt Mar 12, 2025
0ab8b45
merge basic control flow
trdavidt Mar 12, 2025
9e5f117
fix count to 5 test
trdavidt Mar 12, 2025
3036e69
meta: add final documentation
Samir-Rashid Mar 12, 2025
cf28715
tests badge
atar13 Mar 12, 2025
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2 changes: 2 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -26,3 +26,5 @@ Cargo.lock

# temporary files
*.bin

.vscode/
12 changes: 12 additions & 0 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,2 +1,14 @@
# binary-room

[![Tests](https://github.com/Samir-Rashid/binary-room/actions/workflows/cargo_test.yml/badge.svg)](https://github.com/Samir-Rashid/binary-room/actions/workflows/cargo_test.yml)

Binary translator from RISC-V to ARM written in Rust


## Testing

To get all the cross-compiling dependencies, enter the nix shell using `nix develop`.

`cargo test -- --nocapture`

Then run `./run.sh filename` to assemble and run the file.
4 changes: 4 additions & 0 deletions flake.nix
Original file line number Diff line number Diff line change
@@ -1,3 +1,5 @@
# dual cross compile toolchain
# https://github.com/noteed/riscv-hello-asm/blob/main/shell.nix
{
description = "binary-room";

Expand Down Expand Up @@ -35,6 +37,8 @@
];
packages = with pkgs; [
rust-analyzer-nightly
clang-tools
hyperfine # benchmarking tool
];
};
}
Expand Down
9 changes: 9 additions & 0 deletions run.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
#!/usr/bin/env bash

ASM_FILE=$1


aarch64-linux-gnu-as $ASM_FILE -o $ASM_FILE.as
aarch64-linux-gnu-ld $ASM_FILE.as -o $ASM_FILE.bin
./$ASM_FILE.bin
echo $?
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