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add RISC-V support #1

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@niwis niwis commented May 13, 2020

This implements the timing channel attacks on RISC-V. It also adds a configuration for the Ariane SoC.

@niwis niwis changed the base branch from timing to master May 13, 2020 10:38
@niwis niwis changed the base branch from master to timing May 13, 2020 10:40
@xurtis xurtis self-requested a review May 14, 2020 00:07
niwis added 2 commits February 25, 2021 13:53
@niwis
riscv: use rdcycle instead of rdtime
32052a3 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
@niwis
ariane: adjust probe buffer size
23f2d47 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
niwis and others added 10 commits May 31, 2022 22:30
@niwis
side-bench: Remove unused variables
25a2e29 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
@robs-cse
build fixes for post-12.1.0 checkout
8104119 
Signed-off-by: Robert Sison <robert.sison@unimelb.edu.au>
@niwis
Enable cache colouring
1e2fe1b 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
@niwis
riscv: Add context-switch latency channel
443f87d 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
@robs-cse
Merge remote-tracking branch 'robs-cse/riscv-update' into riscv
695f2fd 
Signed-off-by: Robert Sison <robert.sison@unimelb.edu.au>
@robs-cse
Adaptations by @thomasbove to build with kernel image clone feature
84fedde 
Co-authored-by: Thomas Bove <t.bove@student.unsw.edu.au>
Signed-off-by: Robert Sison <robert.sison@unimelb.edu.au>
@robs-cse
Fix misconfiguration of thread domain due to overwriting of argument
866d196 
Co-authored-by: Thomas Bove <t.bove@student.unsw.edu.au>
Signed-off-by: Robert Sison <robert.sison@unimelb.edu.au>
@robs-cse
Assign appropriate domains to trojan and spy depending on KERNEL_IMAGES
b3f74b3 
Signed-off-by: Robert Sison <robert.sison@unimelb.edu.au>
@niwis
riscv: Bringup llc kernel channel
09963ee 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
@niwis
Add LLC shared kernel data channel
3dbfba8 
Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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