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RehanQasim-dev/README.md

Hi there, I'm Rehan Qasim 👋

AI Compiler Engineer @ 10xEngineers | LLM Inference Optimization|Computer Architecture

I specialize in bridging the gap between hardware and software to accelerate AI workloads. My focus is on the RISC-V Software Ecosystem (RISE), creating high-performance kernels for LLM inference.

  • 🔭 Currently working on: RISC-V Vector (RVV) support for llama.cpp and implementing LLM ops kernels for RISC-V vector extension.
  • 🎓 Education: BS Electrical Engineering from UET Lahore (Gold Medalist, Rank 1/200).
  • 🛠️ Tech Stack: C/C++, Python, Machine Learning, RISC-V Assembly, SystemVerilog, FPGA (Vivado).
  • 📫 Connect: LinkedIn | Email

🦙 My llama.cpp Contributions

Recent commits optimizing for RISC-V:

  • d34d5ca1e llamafile: add rvv support for sgemm kernels (#18199)
  • f716588e6 ggml-cpu: extend support for RVV floating-point kernels (#17318)

Popular repositories Loading

  1. RISC-V-GEMM-Coprocessor-for-Edge-AI RISC-V-GEMM-Coprocessor-for-Edge-AI Public

    SystemVerilog 2 2

  2. Single-Cycle-RISCV-32I-Processor Single-Cycle-RISCV-32I-Processor Public

    Sytem verilog code for single cycle RISCV-32I processor.It supports all the base level instructions.

    SystemVerilog 1

  3. CNN_Accelerator CNN_Accelerator Public

    C 1

  4. RVVAutoVectorize RVVAutoVectorize Public

    C++ 1

  5. Words_TimeStamps Words_TimeStamps Public

    Python project to get starting and ending timestamps of each word from audio

    Jupyter Notebook

  6. RISC-V-Single-Cycle-Non-pipelined-Processor-Core RISC-V-Single-Cycle-Non-pipelined-Processor-Core Public

    This is Single cycle RISC_V processor code written in System Verilog to run on FPGAs.

    SystemVerilog