The main goal of this project is to alter the processor to execute both paths of a conditional branch instead of guessing the correct path to increase performance. When the correct path of a branch is determined, then squash the incorrect path. My changes to code are listed below.
to run this 721sim --disambig=0,0,0 --perf=1,1,1,1 -t --fq=64 --cp=32 --al=256 --lsq=128 --iq=64 --iqnp=4 --fw=4 --dw=4 --iw=8 --rw=4 pk if.riscv
Any change that is made to a file will be included with a comment in the file in the following format
"DHP FIX
..."
FETCH STAGE
payload.h
-add a mux flax for CMOV and changing branch instr for decode stage and alu stage.
payload.cc
-add argument flag for inherit prev instruction to map_to_actual depending on DHP region intrs if good or bad
-if inherit prev is true, get prev good instr value and prev db_index to current index and return
btb.h
-add argument Branch_PC to btb lookup
-add argument nomral to do normal btb lookup or sequential variable set
btb.cc
-if pc is hammock pc or we dont want normal call, sequentially set variables and return
-use normal variable for not being in IDLE state.
fetchunit.h
-declare enumerate state_machine control variable
-declare instr counter for instructions in each state
-declare hammock info struct ideal table
fetchunit.cc
-initialize state_machine as IDLE
-define hammock ideal table struct
-call btb lookup with hammock PC argument only if state machine is IDLE
-make switch control in fetch transfer bundle function to map_to_actual based on hammock state branch outcome
-in fetch2 if a mispredict, set state_machine to IDLE again because mispredict is a branch before predicate branch.
decode.cc
-use OP_OP_32 for branch instr
-use OP_OP_IMM_32 for CMOVE instr
-set all source registers to true and destination registers to true and values if mux instr, otherwise do normal
alu.cc
-change OP_OP_32 execution for mux == 1 for a hammock branch instruction that wants a destination reg value to determine
-which reg is true for CMOVE
-change OP_OP_IMM_32 for CMOVE execution in ALU
-if predicate value rs3(D) is nonzero, bring rs1(A) reg value into C, else bring rs2(B) reg value into C
riscv-base decode.h
-provide set functions to inject instructions in Fetch State Machine
RENAME STAGE
pipeline.cc -added 1 log reg to renamer
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(Doesnt Matter Anymore)
payload.h
-Record in fetch1 if instruction is valid predicate instr or not
-Record in fetch1 if instruction is in correct region(true) or dead instruction(false)
-depending on case in transfer_fetch_bundle, set bool for valid predicate or correct_region
///////////////////////
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payload.h
payload.cc
-bool DHP and DHP_id recorded in payload. Instruction is a DHP CD instruction or not and the pReg ID that guards it
fetchunit.cc
-dont set DHP to true for branch or CMOVE, default set to false and set to true if in CD region (not IDLE or CMOV)
rename.cc
-use rename_rsrc to ask what pREG of r64 is and give it to the payload buffer
dispatch.cc
-2 new arguments, pass in bool DHP and uint64_t DHP id to REN->dispatch_inst
-instruction will only set DHP to true if its in DHP CD region
renamer.h
renamer.cc
-3 new fields to active list, DHP (1 or 0), DHP_id value, deactivated (1 or 0)
-add 2 new fields to dispatch instruction DHP, DHP_id in renamer.h renamer.cc
-set fields for active list DHP and DHP_id inside dispatch function set deactivate field to false initially
-add deactivate function for writeback when instruction is DHP and taken,
deactivate instruction that uses its DHP_id and the PC to deactivate.
-commit function looks for DHP and deactivated to be true, and commits differently.
writeback.cc
- if instruction that executed is branch predicate, and its destination value is true;
- call deactivate with its destination tag to deactivate instructions in active list that depend on this tag and
- are a valid DHP instruction