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Welcome to the PCAP-Generator wiki!

This project builds on the previous 2 (I2CMatrix and DP83848) to create a PCAP interface on the LogiPi.

Again the project uses a slightly modified DP83848 development board and this time I used PMOD 2 to ensure a high speed connection to the RMII Interface and allow use of the NC connections for future use.

I have added a FIFO using the LogiPi's on board SDRAM. This FIFO buffer allows for continuous capture of network traffic, whilst the Raspberry Pi SPI Interface allows software to flush the buffer, reading stored packets. The design again uses the Raspberry Pi I2C interface to provide commands and read the status of the DP83848 internal registers via the new PhyRegisters component. PhyRegisters also provides some internal registers to allow the user to read the FIFO read and write pointers, to reset the FIFO and to reset the epoch in the EpochGen block.

The Epoch generator ensures packets are stamped with microsecond accuracy. Note the DP83848 uses the 50Mhz FPGA clock as it's reference to ensure synchronisation.

The RMII Interface buffers Ethernet data and generates a 32 bit wide data bus for writing into the SDRAM FIFO. If left to run the RMII Interface will continue to send data to the FIFO until it is full.

The Raspberry Pi SPI interface allows the user to read FIFO data, incrementing the FIFO read pointer until all data is flushed. The user can also monitor the FIFO read and write pointers via the I2C Interface to prevent buffer overrun.