Release v1.0.0

What's Changed

• feat: add firtool binary for Windows by @Jim-shop in #1
• fix: upgrade chisel version by @rewired-gh in #2
• fix: upgrade other dependencies by @rewired-gh in #3
• Multiple commits by @rewired-gh in #4
• 早期总体设计 by @rewired-gh in #5
• Remove user-specific configs by @rewired-gh in #10
• AXI总线 by @Jim-shop in #8
• Simple Fetch Stage (1) by @rewired-gh in #11
• fix: fully initialize ports in AXI master by @Jim-shop in #13
• Simple top module connections by @rewired-gh in #12
• Dev yhy by @Chrisqcwx in #15
• the rest part of AXI by @Jim-shop in #14
• fix: misc including things related to scoreboard (WIP) by @rewired-gh in #16
• Add AXI crossbar to Simple Fetch Stage by @Jim-shop in #18
• feat: add insts; refactor: exeStage with state machine by @Chrisqcwx in #19
• feat: refactor alu with state machine and avoid recalculating mul/div when stalling by @Chrisqcwx in #20
• fix: chiplab debug port by @rewired-gh in #22
• refactor: rename MemLoadStoreNdPort -> MemLoadStoreInfoNdPort by @Chrisqcwx in #21
• Integrate with Chiplab (in progress) by @Jim-shop in #24
• refactor: refactor Mul module with booth algorithm and wallance tree. by @Chrisqcwx in #25
• Make difftest possible by @rewired-gh in #26
• feat!: add csr and exceptions. MANY ports modified by @Chrisqcwx in #27
• refactor: rename WbDebugPort --> InstInfoPort by @Chrisqcwx in #28
• Upgrade CIRCT related stuff by @rewired-gh in #29
• feat: add many many many CsrRegs ; delect divisorZeroException by @Chrisqcwx in #30
• refactor: move some bundles' location; feat: add csr decode and assign; fix: fix state behavior error in exeStage by @Chrisqcwx in #31
• feat: add scoreboard for csr by @Chrisqcwx in #32
• Baby Step 1: DCache (WIP) by @rewired-gh in #33
• Baby Step 2: DCache (WIP) by @rewired-gh in #34
• Baby Step 3: DCache (WIP) by @rewired-gh in #36
• Project cleanup by @rewired-gh in #37
• fix: bugs from previous refactor by @rewired-gh in #38
• feat: add data forward by @Chrisqcwx in #39
• refactor!!: decode in IssueStage -> decode in InstQueue; jump branch new Pc calc by exe send to Ctrl Unit to decide which new pc by @Chrisqcwx in #41
• Mem stage port by @rewired-gh in #44
• Remove clutters by @rewired-gh in #45
• Mem Stage by @rewired-gh in #46
• Difftest Compatibility (Basic) by @Jim-shop in #40
• (CAN MERGE)remove data forward temporily; feat: add BiInstQueue, BiIssueStage, RobStage; add memAccessPort in ExeStage by @Chrisqcwx in #43
• Memory stage related stuffs (Episode 1) by @rewired-gh in #47
• refactor: adapt to the new MemRequestNdPort (add a port: isUnsigned); fix: fix some bugs in rob by @Chrisqcwx in #48
• refactor: refactor some bundle port with parameters; kill the writeEn when writeAddr is x0 by @Chrisqcwx in #49
• fix: fix Difftest valid signal connection by @Jim-shop in #52
• fix: difftest connections by @rewired-gh in #55
• fix: Bug flush(#51) by @Jim-shop in #54
• (Drafted) Chiplab automation by @rewired-gh in #53
• fix: fix bug in inst sra and bl by @Chrisqcwx in #56
• fix: fix bug in Cu by @Chrisqcwx in #57
• TLB implementation by @rewired-gh in #50
• feat: a little tool for 'rebasing' branch by @rewired-gh in #60
• feat: make 'rebasing' safer by @rewired-gh in #61
• feat: 以黑盒形式接入AXI Crossbar by @Jim-shop in #64
• fix: unmangle most stuffs by @rewired-gh in #66
• Fix comb loop by @rewired-gh in #67
• Remove crossbar connection and fix decode instruction matched by @rewired-gh in #70
• 修Crossbar by @Jim-shop in #71
• 再修 Crossbar by @Jim-shop in #72
• Fix several critical things by @rewired-gh in #73
• Fix PC jump in SimpleFetchStage by @rewired-gh in #76
• fix: something by @rewired-gh in #77
• feat: BaseStage infrastructure by @rewired-gh in #79
• fix: several bugs by @rewired-gh in #80
• Fix ready valid by @Jim-shop in #83
• Dev frontend add ICache and test by @NotTheEndOfTheWorld in #82
• feat: add syscall and brk in ExeStage by @Chrisqcwx in #88
• fix: inst sltui decode err by @Chrisqcwx in #89
• fix: mul & div error; test lab6 success by @Chrisqcwx in #94
• feat: add excp & ertn difftest ; fix typo ; refactor some comments by @Chrisqcwx in #95
• Connect difftest by @rewired-gh in #96
• fix: csr -> instinfo in BiInstQueue by @Chrisqcwx in #99
• Revert "fix: csr -> instinfo in BiInstQueue" by @rewired-gh in #101
• Introduce ICache and fix cache related bugs by @NotTheEndOfTheWorld in #100
• Address translation related by @rewired-gh in #104
• Eliminate memory write structure hazard by @rewired-gh in #106
• fix issue bug & refactor Scoreboard by @Chrisqcwx in #103
• feat: tune params by @rewired-gh in #110
• Fix firtool for debug by @rewired-gh in #111
• Refactor BiIssueStage with MultiBaseStage by @Chrisqcwx in #109
• Fix "divisor greater than dividend" by @rewired-gh in #113
• Fix CSR maintenance instruction implementation by @rewired-gh in #114
• Literally fix csr instruction by @rewired-gh in #116
• Connect difftest csr_rstat by @rewired-gh in #117
• fix ertn bug by @Chrisqcwx in #118
• decode for tlb; refactor csr scoreboard by @Chrisqcwx in #120
• Connect difftest, implement cache maintenance, and refactor DCache to use B...