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I've updated the inputs and outputs to reflect the new one pager, as well as started the logic for it. I've placed comments next to the logics for clarifications. I haven't written down what pc_q should be when redirected, or what inst_o should be ic_rsp_valid_i is not true.
I've turned the always combinational into sequential. I've noted that the pc logic will be handled by the core file, and is now commented out. For the Cache Response Logic, I've set Inst_o to 32'b0 (invalid signal) for now, until I can verify with the decode stage on errors.
Added NOP, which is 32'b0. I've set the first always part to be combinational, and separated !rst_ni and redir_i if statements. For the second always, I've simplified the if statements with redir_i and !ic_rsp_valid_i
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Description
I've finished the prototype of the fetch file, with the inputs, outputs, and logic.
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This code needs to be tested with the testbench.
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