Skip to content

Conversation

@murphe67
Copy link
Collaborator

No description provided.

Copy link
Collaborator

@shundroid shundroid left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Thank you for adding this feature!

Comment on lines +14 to +15
# Run synthesis
synth_design -top $TOP_DESIGN -part xc7k160tfbg484-1 -no_iobuf -mode out_of_context -flatten_hierarchy none
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Do we need to run the synthesis again? I think it's better to use write_checkpoint and read_checkpoint commands if possible:

syntax:

write_checkpoint -force $DIR/impl.dcp

(read_checkpoint: I've never tried)

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

the -flatten_hierarchy none flag means that this synthesis run produces different results to the normal synthesis script (poorer results, but it allows the switching activity annotation)

Copy link
Collaborator

@shundroid shundroid Nov 26, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I wanted to mention the duplication with the synthesis for power estimation, I think it also has the flatten_hierarchy option:

synth_design -top $TOP_DESIGN -part xc7k160tfbg484-1 -no_iobuf -mode out_of_context -flatten_hierarchy none

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

ah, possibly! but we are currently only running synthesis once (some of the simulations were hanging with the double synth option).

I should investigate it though!

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

ah, possibly! but we are currently only running synthesis once (some of the simulations were hanging with the double synth option).

I should investigate it though!

Comment on lines +50 to +59

vhdl_src_folder = os.path.join(output_dir, "hdl")
if not os.path.exists(vhdl_src_folder):
print(f"[ERROR] {vhdl_src_folder} not found. Please run the 'write-hdl' command")
return

tb_file = os.path.join(output_dir, "sim", "HDL_SRC", f"tb_{kernel_name}.vhd")
if not os.path.exists(tb_file):
print(f"[ERROR] {tb_file} not found. Please run the 'simulate' command")
return
Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@shundroid switched so the vhdl files are from the hdl folder, and we pull just the tb file from the sim folder

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants