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@ducky64 ducky64 commented Jan 1, 2026

ducky64/usb-source-measure#7 - slow down control loop (reduce opamp integrator gain), in particular to get it slower than the current sense RC filter. Also renames 'factor' to 'gain' and adds an intuitive meaning of the term in the docs.

ducky64/usb-source-measure#8 - reduce current sense gain to 5x to allow 3A at full scale

ducky64/usb-source-measure#1 - fix ramp at low voltages, previously it was calculating the divider for gate voltage relative to ground, whereas for PMOS it needs to be gate voltage relative to source = Vin.

These have been tested with board component replacements and work.

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Pull request overview

This PR implements three critical fixes for the SMU3.1 (Source Measure Unit) design, addressing stability, measurement range, and PMOS control issues.

Key Changes:

  • Slows down the control loop by reducing opamp integrator gain 10x (1nF→10nF capacitor, gain reduced from ~213kHz to ~21kHz)
  • Reduces current sense gain from 10x to 5x to support full-scale measurement of 3A current
  • Fixes PMOS ramp limiter calculation to correctly compute gate voltage relative to source (Vin) instead of ground

Reviewed changes

Copilot reviewed 5 out of 5 changed files in this pull request and generated 2 comments.

Show a summary per file
File Description
edg/abstract_parts/OpampCircuits.py Renames parameter 'factor' to 'gain' in IntegratorInverting class and updates documentation; removes series and tolerance parameters from constructor
edg/abstract_parts/PowerCircuits.py Corrects RampLimiter PMOS gate voltage divider calculation from target_vgs/Vin to (Vin-target_vgs)/Vin to properly account for source-referenced operation
examples/test_usb_source_measure.py Adjusts RampLimiter target_vgs range from (3.7, 19)V to (3.5, 17.5)V to accommodate corrected calculation
examples/UsbSourceMeasure/UsbSourceMeasure.net Updates component values: swaps ramp divider resistors (220k↔680k), increases integrator capacitor (1nF→10nF), increases current sense gain resistor (5.6k→12k)
examples/UsbSourceMeasure/SourceMeasureControl.kicad_sch Updates schematic property values to reflect parameter renaming (factor→gain) and new component values (10nF capacitor, 5x gain ratio)

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Comment on lines 366 to 367
1/RC is the integrator gain. One intuitive interpretation is, for a DC input,
the time it takes for the output voltage to change by the input voltage.
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The documentation states "for a DC input, the time it takes for the output voltage to change by the input voltage." This explanation is unclear and potentially confusing. For an integrator with gain 1/RC, when a DC input Vin is applied, the output voltage changes at a rate of -Vin/(RC) per second. So the time for the output to change by Vin would be RC seconds, not 1/RC. Consider rephrasing to: "For a DC input, 1/RC represents the rate of change of output voltage per unit input voltage (in Hz or 1/s)." or "For a DC input of 1V, the output changes at 1/RC volts per second."

Suggested change
1/RC is the integrator gain. One intuitive interpretation is, for a DC input,
the time it takes for the output voltage to change by the input voltage.
1/RC is the integrator gain and has units of 1/s. For a DC input, 1/RC
represents the rate of change of output voltage per unit input voltage:
for a DC input of 1 V, the output changes at 1/RC volts per second.

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# because PMOS is source-referenced from vin, calculate the Vgs from GND by subtracting from Vin
# however, we can't calculate a fixed Vgs range for all Vin, since it would be overly restrictive,
# so instead we calculate ratios at the Vin corners, then take the intersection of the ratios
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The calculation may produce unexpected results when target_vgs.upper() exceeds pwr_in.voltage.lower(). In this case, vgs_ratio_low will contain negative values, which may not be properly handled by the resistive divider. Consider adding an assertion or validation to ensure target_vgs.upper() is less than pwr_in.voltage.lower(), or document this as a precondition for using this block.

Suggested change
# so instead we calculate ratios at the Vin corners, then take the intersection of the ratios
# so instead we calculate ratios at the Vin corners, then take the intersection of the ratios
# Precondition: ensure the maximum target Vgs is less than the minimum input voltage so that
# the computed Vgs ratios remain non-negative and are meaningful for the resistive divider.
assert (
self.target_vgs.upper() < self.pwr_in.link().voltage.lower()
), "target_vgs.upper() must be less than pwr_in.voltage.lower()"

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Pull request overview

Copilot reviewed 5 out of 5 changed files in this pull request and generated no new comments.


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@ducky64 ducky64 merged commit 62c42e5 into master Jan 1, 2026
17 of 18 checks passed
@ducky64 ducky64 deleted the smu-fixes branch January 1, 2026 09:17
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2 participants