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53 changes: 26 additions & 27 deletions .github/workflows/pr-python.yml
Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,25 @@
"examples/**.py"
]'

black_latest_3_11:
needs: pre_job
if: ${{ needs.pre_job.outputs.should_skip != 'true' }}
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v1
- uses: actions/setup-python@v1
with:
python-version: '3.11'

- name: install mypy
run: |
pip install -r requirements.txt
pip install black
- name: black
run: black --check .

mypy_latest_3_11:
needs: pre_job

Check warning

Code scanning / CodeQL

Workflow does not contain permissions Medium

Actions job or workflow does not limit the permissions of the GITHUB_TOKEN. Consider setting an explicit permissions block, using the following as a minimal starting point: {contents: read}
if: ${{ needs.pre_job.outputs.should_skip != 'true' }}
runs-on: ubuntu-latest
steps:
Expand All @@ -49,21 +66,6 @@
- name: mypy
run: mypy --install-types .

unittest_latest_3_11:
needs: pre_job
if: ${{ needs.pre_job.outputs.should_skip != 'true' }}
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v1
- uses: actions/setup-python@v1
with:
python-version: '3.11'

- name: install dependencies
run: pip install -r requirements.txt
- name: unittest
run: python -m unittest discover

packagetest_latest_3_11:
needs: pre_job
if: ${{ needs.pre_job.outputs.should_skip != 'true' }}
Expand All @@ -83,23 +85,20 @@
- name: toptest
run: cd examples && python test_blinky.py

mypy_latest_3_9:
unittest_latest_3_11:
needs: pre_job
if: ${{ needs.pre_job.outputs.should_skip != 'true' }}
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v1
- uses: actions/setup-python@v1
with:
python-version: '3.9'
- uses: actions/checkout@v1
- uses: actions/setup-python@v1
with:
python-version: '3.11'

- name: install mypy
run: |
pip install -r requirements.txt
pip install mypy mypy-protobuf
mypy --version
- name: mypy
run: mypy --install-types .
- name: install dependencies
run: pip install -r requirements.txt
- name: unittest
run: python -m unittest discover

unittest_latest_3_9:
needs: pre_job
Expand Down
10 changes: 5 additions & 5 deletions blinky_skeleton.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,11 @@


class BlinkyExample(SimpleBoardTop):
@override
def contents(self) -> None:
super().contents()
# your implementation here
@override
def contents(self) -> None:
super().contents()
# your implementation here


if __name__ == "__main__":
compile_board_inplace(BlinkyExample)
compile_board_inplace(BlinkyExample)
97 changes: 49 additions & 48 deletions edg/BoardCompiler.py
Original file line number Diff line number Diff line change
Expand Up @@ -11,64 +11,65 @@


def compile_board(design: Type[Block], target_dir_name: Optional[Tuple[str, str]]) -> CompiledDesign:
if target_dir_name is not None:
(target_dir, target_name) = target_dir_name
if not os.path.exists(target_dir):
os.makedirs(target_dir)
assert os.path.isdir(target_dir), f"target_dir {target_dir} to compile_board must be directory"
if target_dir_name is not None:
(target_dir, target_name) = target_dir_name
if not os.path.exists(target_dir):
os.makedirs(target_dir)
assert os.path.isdir(target_dir), f"target_dir {target_dir} to compile_board must be directory"

design_filename = os.path.join(target_dir, f'{target_name}.edg')
netlist_filename = os.path.join(target_dir, f'{target_name}.net')
bom_filename = os.path.join(target_dir, f'{target_name}.csv')
svgpcb_filename = os.path.join(target_dir, f'{target_name}.svgpcb.js')
design_filename = os.path.join(target_dir, f"{target_name}.edg")
netlist_filename = os.path.join(target_dir, f"{target_name}.net")
bom_filename = os.path.join(target_dir, f"{target_name}.csv")
svgpcb_filename = os.path.join(target_dir, f"{target_name}.svgpcb.js")

with suppress(FileNotFoundError):
os.remove(design_filename)
with suppress(FileNotFoundError):
os.remove(netlist_filename)
with suppress(FileNotFoundError):
os.remove(bom_filename)
with suppress(FileNotFoundError):
os.remove(svgpcb_filename)
with suppress(FileNotFoundError):
os.remove(design_filename)
with suppress(FileNotFoundError):
os.remove(netlist_filename)
with suppress(FileNotFoundError):
os.remove(bom_filename)
with suppress(FileNotFoundError):
os.remove(svgpcb_filename)

compiled = ScalaCompiler.compile(design, ignore_errors=True)
compiled.append_values(RefdesRefinementPass().run(compiled))
compiled = ScalaCompiler.compile(design, ignore_errors=True)
compiled.append_values(RefdesRefinementPass().run(compiled))

if target_dir_name is not None: # always dump the proto even if there is an error
with open(design_filename, 'wb') as raw_file:
raw_file.write(compiled.design.SerializeToString())
if target_dir_name is not None: # always dump the proto even if there is an error
with open(design_filename, "wb") as raw_file:
raw_file.write(compiled.design.SerializeToString())

if compiled.errors:
from . import core
raise core.ScalaCompilerInterface.CompilerCheckError(f"error during compilation:\n{compiled.errors_str()}")
if compiled.errors:
from . import core

netlist_all = NetlistBackend().run(compiled)
bom_all = GenerateBom().run(compiled)
svgpcb_all = SvgPcbBackend().run(compiled)
assert len(netlist_all) == 1
raise core.ScalaCompilerInterface.CompilerCheckError(f"error during compilation:\n{compiled.errors_str()}")

if target_dir_name is not None:
with open(netlist_filename, 'w', encoding='utf-8') as net_file:
net_file.write(netlist_all[0][1])
netlist_all = NetlistBackend().run(compiled)
bom_all = GenerateBom().run(compiled)
svgpcb_all = SvgPcbBackend().run(compiled)
assert len(netlist_all) == 1

with open(bom_filename, 'w', encoding='utf-8') as bom_file:
bom_file.write(bom_all[0][1])
if target_dir_name is not None:
with open(netlist_filename, "w", encoding="utf-8") as net_file:
net_file.write(netlist_all[0][1])

if svgpcb_all:
with open(svgpcb_filename, 'w', encoding='utf-8') as bom_file:
bom_file.write(svgpcb_all[0][1])
with open(bom_filename, "w", encoding="utf-8") as bom_file:
bom_file.write(bom_all[0][1])

return compiled
if svgpcb_all:
with open(svgpcb_filename, "w", encoding="utf-8") as bom_file:
bom_file.write(svgpcb_all[0][1])

return compiled


def compile_board_inplace(design: Type[Block], generate: bool = True) -> CompiledDesign:
"""Compiles a board and writes the results in a sub-directory
where the module containing the top-level is located"""
designfile = inspect.getfile(design)
if generate:
target_dir_name = (os.path.join(os.path.dirname(designfile), design.__name__), design.__name__)
else:
target_dir_name = None
compiled = compile_board(design, target_dir_name)

return compiled
"""Compiles a board and writes the results in a sub-directory
where the module containing the top-level is located"""
designfile = inspect.getfile(design)
if generate:
target_dir_name = (os.path.join(os.path.dirname(designfile), design.__name__), design.__name__)
else:
target_dir_name = None
compiled = compile_board(design, target_dir_name)

return compiled
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