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Enhance PCIe Test Rule PCI_IN_19 to consider the DPC #192

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Enhance PCIe Test Rule PCI_IN_19 to consider the DPC #192

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84f04c8
fix: Include segment number during bdf check
Dec 17, 2025
3c2f1f6
chore: Add support to disable & re-enable DPC
Dec 17, 2025
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24 changes: 23 additions & 1 deletion test_pool/pcie/p030.c
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Original file line number Diff line number Diff line change
Expand Up @@ -48,6 +48,7 @@ payload(void)
uint32_t bdf;
uint32_t dp_type;
uint32_t dsf_bdf;
uint32_t parent_bdf;
uint32_t pe_index;
uint32_t tbl_index;
uint32_t bar_data;
Expand All @@ -56,6 +57,7 @@ payload(void)
uint64_t bar_base;
uint32_t status;
uint32_t timeout;
uint32_t dpc_trig_val = 0;

pcie_device_bdf_table *bdf_tbl_ptr;

Expand Down Expand Up @@ -104,13 +106,24 @@ payload(void)
val_pcie_get_mmio_bar(bdf, &bar_base);

/* Skip this function if it doesn't have mmio BAR */
val_print(ACS_PRINT_DEBUG, " Bar Base %x", bar_base);
val_print(ACS_PRINT_DEBUG, " Bar Base %x\n", bar_base);
if (!bar_base)
continue;

/* Disable error reporting of this function to the Upstream */
val_pcie_disable_eru(bdf);

if ((dp_type == RP) || (dp_type == DP))
{
/* Disable DPC for the rootport / Dowstream port */
dpc_trig_val = val_pcie_disable_dpc(bdf);
} else if (!val_pcie_parent_is_rootport(bdf, &parent_bdf))
{
/* Disable DPC for the parent rootport */
val_print(ACS_PRINT_DEBUG, "RP BDF = 0x%08x\n", parent_bdf);
dpc_trig_val = val_pcie_disable_dpc(parent_bdf);
}

/*
* Clear unsupported request detected bit in Device
* Status Register to clear any pending urd status.
Expand Down Expand Up @@ -158,6 +171,15 @@ payload(void)
/* Enable memory space access to decode BAR addresses */
val_pcie_enable_msa(bdf);

/* Enable DPC trigger if it was disabled */
if (dpc_trig_val)
{
if ((dp_type == RP) || (dp_type == DP))
val_pcie_enable_dpc(bdf, dpc_trig_val);
else
val_pcie_enable_dpc(parent_bdf, dpc_trig_val);
}

/* Reset the loop variables */
bar_data = 0;
}
Expand Down
2 changes: 2 additions & 0 deletions val/include/val_interface.h
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Original file line number Diff line number Diff line change
Expand Up @@ -270,6 +270,8 @@ void val_pcie_enable_msa(uint32_t bdf);
void val_pcie_clear_urd(uint32_t bdf);
void val_pcie_enable_eru(uint32_t bdf);
void val_pcie_disable_eru(uint32_t bdf);
uint32_t val_pcie_disable_dpc(uint32_t bdf);
void val_pcie_enable_dpc(uint32_t bdf, uint32_t dpc_trig_val);
void val_pcie_get_mmio_bar(uint32_t bdf, void *base);
void val_pcie_read_acsctrl(uint32_t arr[][1]);
void val_pcie_write_acsctrl(uint32_t arr[][1]);
Expand Down
60 changes: 59 additions & 1 deletion val/src/acs_pcie.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1225,6 +1225,63 @@ val_pcie_disable_eru(uint32_t bdf)
val_pcie_write_cfg(bdf, pciecs_base + DCTLR_OFFSET, reg_value & dis_mask);
}

/**
@brief Disable DPC trigger enable bits
@param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
@return DPC trigger enable bits value
**/
uint32_t
val_pcie_disable_dpc(uint32_t bdf)
{
uint32_t dpc_cap_base;
uint32_t reg_value;
uint32_t status;
uint8_t dpc_trig_val;

/* Check DPC capability */
status = val_pcie_find_capability(bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base);
if (status == PCIE_CAP_NOT_FOUND)
{
val_print(ACS_PRINT_DEBUG, "ECID_DPC not found\n", 0);
return 0;
}

/* Disable DPC trigger enable bits */
val_pcie_read_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, &reg_value);
dpc_trig_val = (reg_value >> DPC_CTRL_TRG_EN_SHIFT) & DPC_CTRL_TRG_EN_MASK;
reg_value &= ~(DPC_CTRL_TRG_EN_MASK << DPC_CTRL_TRG_EN_SHIFT);
val_pcie_write_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, reg_value);
return dpc_trig_val;
}

/**
@brief Enable DPC trigger enable bits
@param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
@param dpc_trig_val - DPC trigger enable bits value
@return None
**/
void
val_pcie_enable_dpc(uint32_t bdf, uint32_t dpc_trig_val)
{
uint32_t dpc_cap_base;
uint32_t reg_value;
uint32_t status;

/* Check DPC capability */
status = val_pcie_find_capability(bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base);
if (status == PCIE_CAP_NOT_FOUND)
{
val_print(ACS_PRINT_DEBUG, "ECID_DPC not found\n", 0);
return;
}

/* Enable DPC trigger enable bits */
val_pcie_read_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, &reg_value);
reg_value &= ~(DPC_CTRL_TRG_EN_MASK << DPC_CTRL_TRG_EN_SHIFT);
reg_value |= ((dpc_trig_val & DPC_CTRL_TRG_EN_MASK) << DPC_CTRL_TRG_EN_SHIFT);
val_pcie_write_cfg(bdf, dpc_cap_base + DPC_CTRL_OFFSET, reg_value);
}

/**
@brief Returns whether a device's bit-field passed the compliance check or not.
The device under test is indicated by input bdf.
Expand Down Expand Up @@ -2263,7 +2320,8 @@ val_pcie_parent_is_rootport(uint32_t dsf_bdf, uint32_t *rp_bdf)
/* Check if device is a direct child of this root port */
val_pcie_read_cfg(bdf, TYPE1_PBN, &reg_value);
if ((dsf_bus == ((reg_value >> SECBN_SHIFT) & SECBN_MASK)) &&
(dsf_bus <= ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK)))
(dsf_bus <= ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK)) &&
(PCIE_EXTRACT_BDF_SEG(bdf) == PCIE_EXTRACT_BDF_SEG(dsf_bdf)))
{
*rp_bdf = bdf;
return 0;
Expand Down