Language: ARM7TDMI

[travisgoodspeed]

Close this issue when we support the ARM7TDMI instruction set. Thumb will be supported elsewhere.

Complications:

• Conditions codes in verb names.
• Both little and big endian support.
• Graders
• eoreqs with eq flag between verb and s.

Data operation complications:

• Shifted Registers
• Rotated Immediates
• TEQ, TST, CMP and CMN should always set S flag.
• R15 is PC+8 or PC+12. See 4.5.5.
• Register shift requires bit7 to be zero.

LDR/STR complications:

• ! suffix to imply writeback on a group
• + and - prefix to imply offset addition or subtraction.
• PC-relative complications.
• T suffix on the verb
• groups with [

Sections:

• 4.3 BX
• 4.4 B, BL
• 4.5 Data Processing
• 4.6 PSR Transfer
• 4.7 Multiply, Multiply-Accumulate
• 4.8 Multiply Long and Multiply-Accumulate Long
• 4.9 Single Data transfer
• 4.10 Halfword and Signed Data transfer
• 4.11 Block Data Transfer
• 4.12 Single Data Swap
• 4.13 Software Interrupt
• 4.14 Coprocessor Data Operations
• 4.15 Coprocessor Data Transfers
• 4.16 Coprocessor Register Transfers
• 4.17 Undefined Instructions

[travisgoodspeed]

Basics data operations now work, but shifting is needed. In ARM7TDMI, a register shift looks like this, where the four shift types are lsl, lsr, asr, and ror. Section 4.5.2 describes some awkward edge cases to this, such as that lsr #0 is used to encode lsr #32, which has a zero result but moves a bit into the carry flag.

        00002aa8 2d 51 a0 e1     mov        r5,sp, lsr #0x2

For immediate values, a signed rotation is also very important. See how a2 is rotated so that the 2 becomes the most significant nybble and a becomes the offset.

        00002aac a2 72 a0 e3     mov        r7,#0x2000000a

• Shifting
• Rotated literals.