Request: Add link to docs in README

[parker-research]

If/when docs are available (including a "Getting Started" page), it would be helpful to have it linked in the README.

I'd love to help contribute code if the vision was more clear, in terms of what the use of this project actually looks like. Without that, I'm a bit lost as to how to make sense of it all.

[samitbasu]

Thanks for the note. I am working feverishly to try and get RHDL into shape. I am super excited about it, and believe it will be much easier to use and more powerful than RustHDL was. I hope in the next few weeks to complete the open items and then will start writing/porting the documentation.

I'll leave this issue open until I can get some semblance of intro docs written.

[tmvkrpxl0]

It has been a year since. Is there any update on it?

[samitbasu]

Wow. Time flies. Yes - I discovered the need for another model for the HDL in RHDL to enable various design rule checks and analysis passes. In particular, identification of critical timing paths in a design, and combinatorial pathways. I guess that took much longer than I had thought.

In any case, it's correct now, and the core is not changing. I have a fair part of the widgets (FIFO, bus components, etc) ported from RustHDL to RHDL. I am working through the remaining pieces and upgrading along the way. Documentation is underway, as is the support for generating top level projects that allow you to actually synthesize designs.

At this point, I am targeting a release by the end of May 2025. That would include the docs, examples, tutorials, etc.

[Baker-Tanaka]

I think RHDL is a fantastic project! You mentioned that you aim to release it by the end of May 2025. How is everything coming along? I'm really looking forward to its release!

[samitbasu]

Thanks for the encouragement @Baker-Tanaka ! It goes really well. I had to take a couple of detours. One to come up with a systematic way of documenting cores, and now another to rework one of the analysis engines that had too many false positives and was generating diagnostic output that was incomprehensible. Most of the cores in the FPGA lib look pretty good to me (at least in simulation), and there are now AXI4Lite cores that make SoC designs easier to build. I probably have a few more to go, but things are looking pretty reasonable for a release.

In terms of schedule, I'm obviously behind schedule, but given it's a nights-and-weekends project, that's probably a given. Let's give me another 3-4 weeks to finish the remaining items. So I'll target first-week of July.

[Baker-Tanaka]

Thank you for your response.
The AXI4Lite cores addition is especially exciting—definitely a big help for SoC designs.
I would like to support you in some way, but unfortunately, I do not have experience with FPGAs and I was trying to learn about FPGAs through RHDL. Since I am Japanese, I might be able to help with the translation of documents into Japanese.
Really looking forward to the release!

[brandonros]

https://github.com/samitbasu/rhdl/blob/main/doc/book/src/quickstart.md

Is this the documentation to get started with the "old" https://github.com/samitbasu/rust-hdl and there is nothing yet documented on how to use the "new" rhdl?

[samitbasu]

@brandonros - that's the old docs. New ones to come soon. Fortunately, with rhdl, there is less to cover, since most of it is just Rust. But there is still some stuff to explain.

[brandonros]

@samitbasu

sorry to distract you, curious your thoughts on this

https://github.com/brandonros/sha256_fpga

I'm trying to take "Rust -> Sipeed Tang Nano 20K" and getting hung up on the "Rust -> Verilog -> yosys json" part because of unbound ERROR: Unconstrained IO:o_OBUF_O

Is there a way to hint/suggest in rhdl output bit/pin/width based on board?

[samitbasu]

@brandonros - not entirely sure I understand your question. But I think you are asking how to constrain the design? Since you seem to be OK with sifting through stuff, can you take a look at rhdl-bsp and rhdl-fpga? In rhdl-bsp, there is an integration test in tests that creates a "Fixture" to contain the logic, and bind the pins. I am in the midst of trying to fix some issues in one of the analysis passes, but the rhdl-fpga crate has a bunch of stuff (although your project looks pretty advanced!). And rhdl-bsp is the direction I am going in.

[korken89]

Hi, I came here from Rust-HDL and were looking to give rhdl a try to see how it is in comparison. I found this issue on linking the docs, and am wondering if there has been any progress on this front? Thanks for the effort!

[samitbasu]

Yeah - docs are in the works. I'll try and publish as I go.

[korken89]

I gave a look around in the project, and it seems the BSPs have not yet reached porting time - would you say it is time now to start migrating to rhdl from rust-hdl , for new projects, or should one stay a bit longer on rust-hdl?